Threshold voltage control using channel digital etch
A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
1. A semiconductor structure for fine-tuning a threshold voltage of a nanosheet structure, the semiconductor structure comprising:
a nanosheet stack including a plurality of nanosheet wires formed over a substrate, each of the plurality of nanosheet wires having only one recessed region extending therein; and
a high-k metal gate (HKMG) formed over the nanosheet stack and between the plurality of nanosheet wires such that the HKMG extends into each of the recessed regions of each of the plurality of nanosheet wires.
2. The semiconductor structure of claim 1 , wherein source/drain regions are formed adjacent the nanosheet stack.
3. The semiconductor structure of claim 2 , wherein tunnel spacers are formed above and below proximal and distal ends of the plurality of nanosheet wires.
4. The semiconductor structure of claim 3 , wherein the proximal and distal ends of the plurality of nanosheet wires include notched regions.
5. The semiconductor structure of claim 4 , wherein the notched regions include the HKMG flowed into the recessed regions.
6. The semiconductor structure of claim 5 , wherein the notched regions create a thinner channel region.
7. The semiconductor structure of claim 6 , wherein an inter-layer dielectric (ILD) is in direct contact with the source/drain regions.
8. The semiconductor structure of claim 7 , wherein the tunnel spacers directly contact the source/drain regions.
9. The semiconductor structure of claim 8 , wherein the tunnel spacers are substantially vertically aligned with respect to the substrate.
10. The semiconductor structure of claim 9 , wherein each of the recessed regions is created by removal of oxidation channels.
11. A semiconductor structure for fine-tuning a threshold voltage of a nanosheet structure, the semiconductor structure comprising:
a nanosheet stack including a plurality of nanosheet wires formed over a substrate, each of the plurality of nanosheet wires having only one recessed region extending therein; and
a high-k metal gate (HKMG) formed over the nanosheet stack and between the plurality of nanosheet wires such that the HKMG extends into each of the recessed regions of each of the plurality of nanosheet wires, each of the recessed regions created by removal of oxidation channels.
12. The semiconductor structure of claim 11 , wherein source/drain regions are formed adjacent the nanosheet stack.
13. The semiconductor structure of claim 12 , wherein tunnel spacers are formed above and below proximal and distal ends of the plurality of nanosheet wires.
14. The semiconductor structure of claim 13 , wherein the proximal and distal ends of the plurality of nanosheet wires include notched regions.
15. The semiconductor structure of claim 14 , wherein the notched regions include the HKMG flowed into the recessed regions.
16. The semiconductor structure of claim 15 , wherein the notched regions create a thinner channel region.
17. The semiconductor structure of claim 16 , wherein an inter-layer dielectric (ILD) is in direct contact with the source/drain regions.
18. The semiconductor structure of claim 17 , wherein the tunnel spacers directly contact the source/drain regions.
19. The semiconductor structure of claim 18 , wherein the tunnel spacers are substantially vertically aligned with respect to the substrate.
20. The semiconductor structure of claim 11 , wherein the oxidation channels were formed on only either a top side or a bottom side of each of the plurality of nanosheet wires.