IP Library › Granted Patent US 11,211,287
Granted Patent B2
US 11,211,287 · App. 16/517,903 · Granted Dec 28, 2021

Semiconductor device and method for fabricating the same

Inventors: Tse-Yao Huang (Taipei, TW); Shing-Yih Shih (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/764H01L21/02123H01L21/02381H01L21/50H01L23/10H01L23/5226
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Quick Facts
Patent No.
US 11,211,287
App. No.
16/517,903
Granted
Dec 28, 2021
Kind
B2
Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.

Claims (34)

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of first set conductive elements separately positioned above the semiconductor substrate;

a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements;

a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks; and

a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks,

wherein a top end of each of the plurality of spaces is lower than top ends of the plurality of first set conductive elements and top ends of the plurality of first set supporting pillars;

wherein each of the plurality of spaces are in contact with a sidewall of one of the plurality of first set conductive elements and a sidewall of one of the plurality of first set supporting pillars.

2. The semiconductor device of claim 1 , further comprising a first sealing layer, wherein the first sealing layer is positioned above the plurality of first set conductive elements.

3. The semiconductor device of claim 2 , wherein the first sealing layer is formed of silicon oxide, silicon nitride, spin-on glass, silicon oxynitride, or silicon nitride oxide.

4. The semiconductor device of claim 2 , wherein the first sealing layer comprises a plurality of protrusions occupying top portions of the plurality of spaces.

5. The semiconductor device of claim 4 , wherein a bottom end of the plurality of protrusions is lower than a top end of the plurality of first set conductive elements.

6. The semiconductor device of claim 1 , wherein the plurality of first set conductive elements are formed of metal, metal alloy, silicate, silicide, polysilicon, or amorphous silicon.

7. The semiconductor device of claim 1 , wherein the plurality of first set supporting pillars are formed of an undoped oxide.

8. The semiconductor device of claim 1 , wherein a width of one of the plurality of spaces is less than or equal to one-fourth of a horizontal distance between an adjacent pair of the plurality of first set conductive elements.

9. The semiconductor device of claim 1 , wherein the plurality of first set supporting pillars and the plurality of insulating blocks are made of undoped oxide.

10. The semiconductor device of claim 9 , further comprising a plurality of first conductive vias, wherein the plurality of first conductive vias are disposed between the plurality of first set conductive elements and the semiconductor substrate and electrically connected to the plurality of first set conductive element, wherein a horizontal distance between one of the plurality of first conductive vias and an adjacent one of the plurality of spaces is less than about 50 nm.

11. A semiconductor device, comprising:

a semiconductor substrate;

a first conductive element positioned above the semiconductor substrate; a second conductive element positioned above the semiconductor substrate and separated from the first conductive element;

an insulating block positioned above the semiconductor substrate and between the first conductive element and the second conductive element;

a third conductive element positioned above the semiconductor substrate and opposite to the first conductive element with the second conductive element interposed therebetween;

a first supporting pillar positioned above the insulating block and between the first conductive element and the second conductive element;

a first space positioned above the insulating block and between the first conductive element and the first supporting pillar; and

a second space positioned above the insulating block and between the second conductive element and the first supporting pillar,

wherein top ends of the first space and the second space are lower than a top end of the first conductive elements and a top end of the first supporting pillar;

wherein the first space is in contact with a sidewall of the first conductive element and a sidewall of the first supporting pillar, and the second space is in contact with a sidewall of the second conductive element and another sidewall of the first supporting pillar.

12. The semiconductor device of claim 11 , wherein the first conductive element is formed of metal, metal alloy, silicate, silicide, polysilicon, or amorphous silicon.

13. The semiconductor device of claim 11 , wherein the first supporting pillar and the insulating block are formed of an undoped oxide.

14. The semiconductor device of claim 11 , further comprising a first sealing layer, wherein the first sealing layer is positioned above the first conductive element, the second conductive element, the third conductive element, and the first supporting pillar.

15. The semiconductor device of claim 14 , wherein the first sealing layer is formed of silicon oxide, silicon nitride, spin-on glass, silicon oxynitride, or silicon nitride oxide.

16. The semiconductor device of claim 14 , wherein the first sealing layer comprises a plurality of protrusions occupying top portions of the plurality of spaces.

17. The semiconductor device of claim 16 , wherein a bottom end of the plurality of protrusions is lower than a top end of the plurality of first set conductive elements.

18. The semiconductor device of claim 11 , wherein a width of the first space is less than or equal to one-fourth of a horizontal distance between the first conductive element and the second conductive element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2019
From: HUANG, TSE-YAO; SHIH, SHING-YIH
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 050000/0627 →
Continuity (1)
Related Publication 20210028053A1 · Jan 28, 2021
Cited By (1)
US 12,232,312