Method for forming a low-k spacer
The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.
1. A method for forming a semiconductor device, the method comprising:
forming a gate stack comprising an upper surface and a sidewall surface;
forming a first spacer on the upper surface and the sidewall surface of the gate stack;
forming a second spacer over the first spacer;
treating the second spacer with a plasma at a first temperature for a first period of time;
treating the second spacer with a gas at a second temperature for a second period of time; and
replacing the gate stack with a metal gate stack, wherein the metal gate stack is formed over a fin active region.
2. The method of claim 1 , wherein the forming the first spacer comprises depositing the first spacer with an atomic layer deposition (ALD) process.
3. The method of claim 1 , wherein the first spacer comprises silicon (Si), oxygen (O), nitrogen (N), and carbon (C).
4. The method of claim 1 , wherein the forming the second spacer comprises depositing the second spacer with an ALD process.
5. The method of claim 1 , wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).
6. The method of claim 1 , wherein the second spacer has a dielectric constant less than about 4.0.
7. The method of claim 1 , wherein the first spacer and the second spacer each has a thickness between about 35 Å and about 45 Å.
8. The method of claim 1 , wherein the plasma comprises a helium (He) plasma.
9. The method of claim 1 , wherein the gas comprises nitrogen (N 2 ) or hydrogen (H 2 ).
10. The method of claim 1 , wherein the second temperature is higher than the first temperature.
11. The method of claim 1 , wherein the gate stack comprises a metal layer and a dielectric layer.
12. The method of claim 1 , wherein the treating the second spacer with the plasma comprises forming Si—O—Si—C cage-link bonds in the second spacer.
13. A method for forming a semiconductor device, the method comprising:
forming a gate stack comprising an upper surface and a sidewall surface;
depositing a first spacer with a first atomic layer deposition (ALD) process at a first temperature for a first period of time, wherein the first spacer covers the upper surface and the sidewall surface of the gate stack; and
forming a second spacer over the first spacer, wherein the forming the second spacer comprises:
depositing the second spacer with a second ALD process at a second temperature for a second period of time;
treating the second spacer with a helium (He) plasma at a third temperature for a third period of time; and
annealing the second spacer with a nitrogen (N 2 ) gas at a fourth temperature for a fourth period of time.
14. The method of claim 13 , wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).
15. The method of claim 13 , wherein the second spacer has a dielectric constant less than about 4.0.
16. The method of claim 13 , wherein the first spacer and the second spacer each has a thickness between about 35 Å and about 45 Å.
17. A method for forming a semiconductor device, the method comprising:
forming a fin with an upper surface and a sidewall surface;
depositing a first spacer to cover the upper surface and the sidewall surface of the fin;
depositing a second spacer over the first spacer;
treating the second spacer with a helium (He) plasma at a first temperature; and
annealing the second spacer with a nitrogen (N 2 ) gas at a second temperature.
18. The method of claim 17 , wherein the second spacer has a thickness between about 35 Å and about 45 Å and a dielectric constant less than about 4.0.
19. The method of claim 17 , wherein the treating the second spacer with the He plasma comprises forming Si—O—Si—C cage-link bonds in the second spacer.
20. The method of claim 17 , wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).