Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture
A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4 F 2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.
1. A method for fabricating an array of memory devices, a memory device of the array of memory devices comprising a two-terminal resistive switching device positioned electrically in parallel to a transistor, comprising:
providing a substrate having an array of buried wordline transistors formed in the substrate, and having a dielectric layer formed over the substrate, wherein the transistor is a member of the array of buried wordline transistors;
forming trenches through the dielectric layer exposing source and drain terminals of the transistors;
filling the trenches with conductive material to form first electrodes that electrically contact source or drain terminals of the transistors;
etching back and smoothing a top surface of the conductive material and dielectric layer;
forming a hardmask over the top surface of the conductive material and dielectric layer;
forming a second dielectric over the hardmask and etching second trenches through the second dielectric offset a distance from the trenches;
forming a switching layer over exposed surfaces of the second trenches;
depositing second conductive material over the switching layer and filling the second trenches with the second conductive material;
removing second conductive material and second dielectric material to expose the hardmask to form second electrodes within the second trenches;
forming a third dielectric over the first electrodes, switching layer and second electrodes;
forming third trenches in the third dielectric;
filling the third trenches with a third conductive material;
smoothing a top surface of the third conductive material and the third dielectric to form conductive contacts within the third trenches;
forming vertical contacts connected respectively at a first end and a second end of the array of transistors; and
forming a first metal line connected to a first of the vertical contacts and a second metal line connected to a second of the vertical contacts.
2. The method of claim 1 , wherein forming the third trenches in the third dielectric further comprises forming the third trenches offset a second distance from the second trenches.
3. The method of claim 2 , wherein the second distance between the third trenches and the second trenches is ½F or about ½F.
4. The method of claim 2 , wherein a trench of the third trenches exposes a portion of one of the second electrodes, a portion of the switching layer and a portion of one of the first electrodes.
5. The method of claim 1 , further comprising removing the hardmask before forming the third dielectric over the first electrodes.
6. The method of claim 1 , wherein forming the third trenches in the third dielectric further comprises forming the third trenches over or approximately over the second trenches.
7. The method of claim 6 , wherein a trench of the third trenches is etched through a portion of one of the second electrodes, a portion of the switching layer and a portion of one of the first electrodes.
8. The method of claim 6 , wherein the conductive contacts are respectively in electrical contact with one of the source and drain terminals of the transistors.
9. The method of claim 6 , wherein a conductive contact of the conductive contacts is connected to a source of a transistor of the transistors and to a bottom electrode of one of the two-terminal resistive switching devices.
10. The method of claim 9 , wherein a second conductive contact of the conductive contacts is connected to a drain of the transistor of the transistors and to a top electrode of the one of the two-terminal resistive switching devices.
11. A method for fabricating an array of memory devices, a memory device of the array of memory devices comprising a two-terminal resistive switching device positioned electrically in parallel to a transistor, comprising:
providing a substrate having an array of buried wordline transistors formed in the substrate, and having a dielectric layer formed over the substrate, wherein the transistor is a member of the array of buried wordline transistors;
forming trenches through the dielectric layer exposing source and drain terminals of the transistors;
filling the trenches with conductive material to form first electrodes that electrically contact source or drain terminals of the transistors;
etching back and smoothing a top surface of the conductive material and dielectric layer;
forming a hardmask over the top surface of the conductive material and dielectric layer;
forming a second dielectric over the hardmask and etching second trenches through the second dielectric offset a distance from the trenches;
forming a switching layer over exposed surfaces of the second trenches;
depositing second conductive material over the switching layer and filling the second trenches with the second conductive material;
removing second conductive material and second dielectric material to expose the hardmask to form second electrodes within the second trenches;
forming a third dielectric over the first electrodes, switching layer and second electrodes;
forming third trenches in the third dielectric;
stopping formation of the third trenches in the third dielectric in response to exposing at least a surface of the second electrodes through the third dielectric;
filling the third trenches with a third conductive material; and
smoothing a top surface of the third conductive material and the third dielectric to form conductive contacts within the third trenches.
12. The method of claim 11 , wherein formation of the third trenches exposes the surface of the second electrodes, a portion of the switching layer and a second surface of the first electrodes.
13. The method of claim 11 , wherein the distance is ½F or about ½F of a photolithographic process employed for etching the second trenches.
14. The method of claim 11 , wherein the third conductive material contacts the surface of the second electrodes exposed through the third dielectric by the third trenches.
15. The method of claim 11 , wherein the second trenches are offset the distance from the trenches by ½F or about ½F and the third trenches are offset from the second trenches by ½F or about ½F.
16. A method for fabricating an array of memory devices, a memory device of the array of memory devices comprising a two-terminal resistive switching device positioned electrically in parallel to a transistor, comprising:
providing a substrate having an array of buried wordline transistors formed in the substrate, and having a dielectric layer formed over the substrate, wherein the transistor is a member of the array of buried wordline transistors;
forming trenches through the dielectric layer exposing source and drain terminals of the transistors;
filling the trenches with conductive material to form first electrodes that electrically contact source or drain terminals of the transistors;
etching back and smoothing a top surface of the conductive material and dielectric layer;
forming a hardmask over the top surface of the conductive material and dielectric layer;
forming a second dielectric over the hardmask and etching second trenches through the second dielectric offset a distance from the trenches;
forming a switching layer over exposed surfaces of the second trenches;
depositing second conductive material over the switching layer and filling the second trenches with the second conductive material;
removing second conductive material and second dielectric material to expose the hardmask to form second electrodes within the second trenches;
forming a third dielectric over the first electrodes, switching layer and second electrodes;
forming third trenches in the third dielectric;
stopping formation of the third trenches in the third dielectric in response to exposing a surface of the first electrodes overlying the source or drain terminals of the transistors through the third dielectric and through a portion of the second electrodes;
filling the third trenches with a third conductive material; and
smoothing a top surface of the third conductive material and the third dielectric to form conductive contacts within the third trenches.
17. The method of claim 16 , wherein the third conductive material physically contacts the surface of the first electrodes overlying the source or drain terminals of the transistors.
18. The method of claim 16 , wherein the distance is ½F or about ½F of a photolithographic process employed for etching the second trenches.
19. The method of claim 16 , wherein the second conductive material is selected to contain filament forming ions that are provided to the switching layer in response to a voltage applied across the two-terminal resistive switching device.
20. The method of claim 16 , wherein the second trenches are offset the distance from the trenches by ½F or about ½F and the third trenches are offset from the second trenches by ½F or about ½F.