IP Library Granted Patent US 11,063,129
Granted Patent B2
US 11,063,129 · App. 16/521,777 · Granted Jul 13, 2021

Self-limiting fin spike removal

Inventors: Kangguo Cheng (Schenectady, NY); Choonghyun Lee (Rensselaer, NY); Juntao Li (Cohoes, NY); Peng Xu (Santa Clara, CA)
Assignee: ELPIS TECHNOLOGIES INC.
H01L29/41791H01L21/324H01L21/76229H01L21/823431H01L29/1054H01L29/6681H01L29/66795H01L29/785H01L29/7851
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Quick Facts
Patent No.
US 11,063,129
App. No.
16/521,777
Granted
Jul 13, 2021
Kind
B2
Abstract

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.

Claims (10)

1. A semiconductor structure, comprising:

a substrate;

one or more fin regions each overlaying a silicon germanium strain relaxed buffer region contacting the substrate and extending in a first direction, the fin region at least partially comprising silicon germanium and silicon oxide converted from silicon germanium, wherein the fin region is formed by laterally forming a germanium oxide spacer on a side of the silicon fin region in the first direction;

a shallow trench isolation region contacting the substrate and between the one or more fin regions; and

a divot in a surface of the substrate, the divot in direct contact with a base of a first fin region of the one or more fin regions, the divot undercutting a sidewall of the first fin region.

2. The semiconductor structure of claim 1 , wherein the fin region is further formed by performing a thermal anneal on the semiconductor structure.

3. The semiconductor structure of claim 2 , wherein the fin region is further formed by performing an etch to remove silicon oxide and a silicon germanium area with a high percentage of germanium formed by the thermal anneal.

4. The semiconductor structure of claim 3 , wherein performing the etch comprises performing an isotropic etch to remove the silicon oxide.

5. The semiconductor structure of claim 2 wherein the thermal anneal is performed in an inert gas environment.

6. The semiconductor structure of claim 5 , wherein the thermal anneal converts at least part of the silicon germanium in the fin to silicon oxide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 054476/0046 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2019
From: CHENG, KANGGUO; LEE, CHOONGHYUN; LI, JUNTAO; XU, PENG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049861/0448 →
Continuity (2)
Division 15890671 · Feb 7, 2018
Related Publication 20190348513A1 · Nov 14, 2019