Image sensor having P-type isolation structure

1. An image sensor comprising:

a first active region including a first floating diffusion region, a first transistor active region including a first drive transistor and a first select transistor, and a first isolation structure for electrically isolating the first floating diffusion region from the first transistor active region,

wherein the first isolation structure comprises a first P-typed doped region disposed on one corner of the first active region and a second P-typed doped region disposed in a center of the first active region, the first P-typed doped region and the second P-typed doped region being electrically coupled to each other and the first P-typed doped region including a contact structure configured to receive a ground voltage,

wherein the first active region further comprises a first transfer transistor region disposed between the first floating diffusion region and the first P-typed doped region, and

wherein a source region of the first select transistor is electrically isolated from the first transfer transistor region by the first P-typed doped region,

wherein a protruding portion of the first floating diffusion region abuts receding portions extended from the first isolation structure, and

wherein the receding portions extended from the first isolation structure include a first extension that is extended and disposed between the first floating diffusion region of the first active region and a drain region of the first drive transistor and between the first isolation structure and a drain region of the first drive transistor.

2. The image sensor of claim 1 , wherein the first transistor active region further comprises:

a channel region, a drain region, and a source region of the first drive transistor; and

a channel region of the first select transistor.

3. The image sensor of claim 2 , wherein the second P-typed doped region abuts the first floating diffusion region, the drain region and the source region of the first drive transistor, and the source region of the first select transistor.

4. The image sensor of claim 2 , wherein the second P-typed doped region is surrounded by the first floating diffusion region, the channel region, the drain region and the source region of the first drive transistor, the channel region and the source region of the first select transistor, and the first P-typed doped region.

5. The image sensor of claim 2 , wherein the first isolation structure further comprises a third P-type doped region which is electrically coupled to the second P-typed doped region, and

the third P-type doped region is disposed between the first floating diffusion region and the first transistor active region.

6. The image sensor of claim 1 , further comprising second to fourth active regions disposed in different locations relative to the first active region,

wherein the second to fourth active regions includes, respectively, second to fourth floating diffusion regions, second to fourth transistor active regions, and second to fourth isolation structures for electrically isolating the second to fourth floating diffusion regions from corresponding transistor active regions.

7. The image sensor of claim 6 , wherein one of the second and third transistor active regions of the second and third active regions comprise:

a channel region, a drain region and a source region of a corresponding drive transistor; and

a channel region and a source region of a corresponding select transistor.

8. The image sensor of claim 6 , wherein one of the second and third isolation structures of the second and third active regions includes a doped region located relative to a corresponding floating diffusion region and abutting the corresponding floating diffusion region, a drain region and a source region of a corresponding drive transistor, and a source region of a corresponding select transistor.

9. The image sensor of claim 6 , wherein one of the second and third isolation structures of the second and third active regions includes a doped region located relative to a corresponding floating diffusion region and surrounded by the corresponding floating diffusion region, a channel region, a drain region and a source region of a corresponding drive transistor, and a channel region and a source region of a corresponding select transistor.

10. The image sensor of claim 6 , wherein the fourth transistor active region of the fourth active region comprises a channel region, a drain region and a source region of a reset transistor.

11. The image sensor of claim 10 , wherein the fourth isolation structure of the fourth active region includes a fourth doped region located relative to a corresponding floating diffusion region and abutting the corresponding floating diffusion region and the drain region and the source region of the reset transistor.

12. The image sensor of claim 11 , wherein the fourth doped region of the isolation structure of the fourth active region is surrounded by the corresponding floating diffusion region, the channel region, and the drain region and the source region of the reset transistor.

13. The image sensor of claim 1 , wherein the first active region is surrounded and defined by a trench isolation structure.

14. An image sensor comprising:

first to fourth active regions comprising first to fourth floating diffusion regions, first to fourth transistor active regions, and first to fourth P-type isolation structures, the first to fourth floating diffusion region being electrically isolated from the first to fourth transistor active regions, respectively, by corresponding ones of the first to fourth P-type isolation structures,

wherein the first to third transistor active regions comprise first to third drive transistors and first to third select transistors, each drive transistor comprising a drain region and a source region and each select transistor comprising a source region, and

the fourth transistor active region comprises a drain region and a source region of a reset transistor, and

wherein the first to fourth P-type isolation structures include contact structures configured to receive a ground voltage,

wherein the first to third transistor active regions comprise first transfer transistor regions, respectively, the first transfer transistor regions disposed between one of the first to third floating diffusion regions and one of the first to third P-type isolation structures, and

wherein source regions of the first to third select transistors are electrically isolated from corresponding first transfer transistor regions, respectively, by corresponding ones of the first to third P-type isolation structures,

wherein first to fourth protruding portions of the first to fourth floating diffusion regions abut first to fourth receding portions extended from the first to fourth P-type isolation structures, and

wherein the first receding portion extended from the first P-type isolation structure includes a first extension that is extended and disposed between the first floating diffusion region of the first active region and the drain region of the first drive transistor and between the first isolation structure and the drain region of the first drive transistor,

wherein the second receding portion extended from the second P-type isolation structure includes a second extension that is extended and disposed between the second floating diffusion region of the second active region and the drain region of the second drive transistor and between the second isolation structure and the drain region of the second drive transistor,

wherein the third receding portion extended from the third P-type isolation structure includes a third extension that is extended and disposed between the third floating diffusion region of the third active region and the drain region of the third drive transistor and between the third isolation structure and the drain region of the third drive transistor, and

wherein the fourth receding portion extended from the fourth P-type isolation structure includes a fourth extension that is extended and disposed between the fourth floating diffusion region of the fourth active region and the source region of the reset transistor and between the fourth isolation structure and the source region of the reset transistor.

15. The image sensor of claim 14 , wherein one of the first to fourth P-type isolation structures comprise a first doped region disposed on one corner of a corresponding one of the first to fourth active regions and a second doped region disposed in a center of the corresponding one of the first to fourth active regions, the first doped region and the second doped region electrically coupled each other.

16. The image sensor of claim 15 , wherein the first doped region of the one of the first to fourth P-type isolation structures abuts one of the source regions of corresponding ones of the first to third select transistors, and

the second doped region of the one of the first to fourth P-type isolation structure abuts the drain region of the reset transistor.

17. The image sensor of claim 15 , wherein the one of the first to fourth P-type isolation structures further comprise a third doped region which abuts the second doped region of the center of the corresponding one of the first to fourth active regions and a corresponding side of the first to fourth active regions.

18. The image sensor of claim 17 , wherein the third doped region is disposed between a corresponding one of the first to third floating diffusion regions and a drain region of a corresponding one of the first to third drive transistors, or

the third doped region is disposed between the fourth floating diffusion region and the source region of the reset transistor.

19. The image sensor of claim 14 , wherein one of the first to third transistor active regions further comprise a channel region of a corresponding one of the first to third drive transistors and a channel region of a corresponding one of the first to third select transistors, and

the fourth transistor active region further comprises a channel region of the reset transistor.

20. An image sensor comprising:

first to fourth active regions comprising first to fourth floating diffusion regions, first to fourth transistor active regions, and first to fourth P-type isolation structures, the first to fourth floating diffusion region being electrically isolated from the first to fourth transistor active regions, respectively, by corresponding ones of the first to fourth P-type isolation structures,

wherein the first to third transistor active regions comprise first to third drive transistors and first to third select transistors, each drive transistor comprising a drain region and a source region and each select transistor comprising a source region,

wherein the fourth transistor active region comprises a drain region and a source region of a reset transistor, and

wherein the first to fourth P-type isolation structures include contact structures configured to receive a ground voltage,

wherein the first to third transistor active regions comprise first transfer transistor regions, respectively, the first transfer transistor regions disposed between one of the first to third floating diffusion regions and one of the first to third P-type isolation structures,

wherein source regions of the first to third select transistors are electrically isolated from corresponding first transfer transistor regions, respectively, by corresponding ones of the first to third P-type isolation structures, wherein one of the first to third transistor active regions further comprise a channel region of a corresponding one of the first to third drive transistors and a channel region of a corresponding one of the first to third select transistors, and

wherein the fourth transistor active region further comprises a channel region of the reset transistor,

wherein the channel region of the corresponding one of the first to third drive transistors, the channel region of the corresponding one of the first to third select transistors, and a corresponding one of the first to third floating diffusion regions are disposed on corners of the one of the first to third active regions, respectively, and

the channel region and the drain region of the reset transistor and the fourth floating diffusion region are disposed on corners of the fourth active region, respectively.