Seismic detection switch
A seismic switch (SS) that is able to detect and signal when internal faults have occurred within the SS is described. The SS provides safety class functionality to the detection of seismic activity. For example, the SS may detect earthquakes above a specified level, resulting in the disconnection of electrical power to a radioactive waste storage facility, which could result in the ignition of waste materials should the storage facility and/or storage container fail during a seismic event. By reducing the risk of fire under these circumstances, the possibility of offsite releases is significantly reduced.
1. A digital seismic switch, comprising:
a first processor;
a second processor, wherein the first processor and the second processor are configured to operate in lockstep and process identical data, and wherein the first and the second processor are configured to detect operational failure of the seismic switch in real time in response to a discrepancy between the first processor and the second processor;
at least one accelerometer configured to detect ground accelerations caused by seismic activity in a frequency range; and
a plurality of peripheral components coupled to the first processor and the second processor, wherein each peripheral component of the plurality of peripheral components includes an error signaling component (ESM) configured to communicate fault associated with its respective peripheral component to the first and the second processors, wherein the plurality of peripheral components includes an analog to digital convertor (ADC) component configured to convert analog values to digital values, a direct memory access (DMA) component configured to control data transfer to and from other memory components, a virtual interrupt (VIM) component configured to control interrupts to the first and the second processors, and an error correct and detection component configured to validate data in a flash memory.
2. The seismic switch of claim 1 , wherein the frequency range is from about direct current (DC) to about 2 KHz or from about 2 Hz to about 15 Hz.
3. The seismic switch of claim 1 , wherein the at least one accelerometer is configured to provide data to a serial peripheral interface (SPI) of the second processor.
4. The seismic switch of claim 3 , wherein:
the at least one accelerometer comprises a first accelerometer comprising three axis balance arms; and
the first accelerometer, when activated via the SPI, places an electrostatic charge on the three axis balance arms to simulate an acceleration signal.
5. The seismic switch of claim 1 , wherein the at least one accelerometer is configured for output comparison for fault detection.
6. The seismic switch of claim 1 , wherein:
the at least one accelerometer is further configured to measure an internal temperature of the seismic switch; and
the internal temperature indicates a fault when the internal temperature is outside of predetermined limits.
7. The seismic switch of claim 1 , wherein the at least one accelerometer comprises a hardware pin connector enabling connection of an external logic analyzer for diagnosis and fault detection.
8. The seismic switch of claim 1 , wherein:
the at least one accelerometer comprises a first accelerometer; and
the first accelerometer is powered by a 3.3 V power supply that is regulated down to a first 1.8 V power supply and a second 1.8 V power supply within the first accelerometer, the first 1.8 V power supply being provided to an analog circuit within the first accelerometer, the second 1.8 V power supply being provided to a digital circuit within the first accelerometer.
9. The seismic switch of claim 1 , further comprising:
a fiber optic connector that couples the seismic switch to a seismic switch remote status (SSRS) display.
10. The seismic switch of claim 1 , further comprising:
a deterministic real time operating system (RTOS) configured to perform safety functions in a period of time prior to performing non-safety functions.
11. The seismic switch of claim 1 , further comprising:
a communication interface with a seismic switch remote status (SSRS) display configured to provide non-safety pre-fault monitoring,
wherein warnings are sent via the communication interface to the SSRS display prior to a complete fault shutdown of the seismic switch.
12. The seismic switch of claim 1 , wherein the safety processor is further configured to perform at least one of:
detection of corrupted data in an analog-to-digital (ADC) data buffer; or
detection of calibration errors in the ADC data buffer.
13. The seismic switch of claim 1 , wherein the second processor is further configured to detect internal power supply voltage errors.
14. The seismic switch of claim 1 , wherein the second processor is further configured to detect out of tolerance output relay drive currents.
15. The seismic switch of claim 1 , wherein the second processor is further configured to detect a stuck on output relay driver.
16. The seismic switch of claim 1 , wherein the second processor is further configured to detect at least one of a corrupted power supply calibration or a corrupted configuration setting.
17. The seismic switch of claim 1 , wherein the second processor is further configured to detect at least one of an out of tolerance main clock or an output of tolerance phase lock loop (PLL).
18. The seismic switch of claim 1 , wherein the second processor is further configured to detect and correct 1 bit memory errors.
19. The seismic switch of claim 1 , wherein the second processor is further configured to detect uncorrectable at least 2 bit memory errors.
20. A digital seismic switch, comprising:
a first processor;
a second processor, wherein the first processor and the second processor are configured to operate in lockstep and process identical data, and wherein the first and the second processor are configured to detect operational failure of the seismic switch in real time in response to a discrepancy between the first processor and the second processor;
at least one accelerometer configured to detect ground accelerations caused by seismic activity in a frequency range;
a plurality of peripheral components coupled to the first processor and the second processor, wherein each peripheral component of the plurality of peripheral components includes an error signaling component (ESM) configured to communicate fault associated with its respective peripheral component to the first and the second processors; and
a self-test controller (STC) configured to perform programmable hardware based test during normal system operations.