Semiconductor device
Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device ( 100 ) includes a semiconductor element ( 50 ) and a control element ( 150 ) arranged on a front surface ( 50 a ) of the semiconductor element ( 50 ). The semiconductor element ( 50 ) includes a semiconductor substrate (SB) including a first region AR 1 and a second region AR 2 adjacent to each other, a first MOS transistor (Tr 1 ) provided is the first region (AR 1 ), and a second MOS transistor (Tr 2 ) provided in the second region (AR 2 ). A first drain region ( 3 a ) of the first MOS transistor (Tr 1 ) is connected to a second drain region ( 3 b ) of the second MOS transistor (Tr 2 ). The control element ( 150 ) turns on and off the first MOS transistor (Tr 1 ) and the second MOS transistor (Tr 2 ).
1. A semiconductor device, comprising:
a semiconductor element; and
a control element arranged on one surface side of the semiconductor element, wherein, the semiconductor element includes
a semiconductor substrate including a first region and a second region adjacent to each other,
a first transistor, provided in the first region, having a first source region and a first drain region,
a second transistor, provided in the second region, having a second source region and a second drain region,
a drain electrode pad provided in the first region and arranged on the one surface side of the semiconductor element, the drain electrode pad being electrically connected to the first source region of the first transistor, and
a source electrode pad provided in the second region and arranged on the one surface side of the semiconductor element, the source electrode pad being arranged away from the drain electrode pad and being electrically connected to the second source region of the second transistor, and
wherein
the first drain region of the first transistor is connected to the second drain region of the second transistor, the first drain region being integrated with the second drain region, and
the control element is configured to turn on and off the first transistor and the second transistor,
the control element is arranged on a drain electrode and a source electrode through a protecting film, and
the control element is arranged to be offset from a space between the drain electrode pad and the source electrode pad.
2. The semiconductor device according to claim 1 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element,
the second source region is of the first conductivity type and arranged on the one surface side of the semiconductor element,
the first transistor further includes a first semiconductor region of the first conductivity type arranged away from the first source region, and a first well region of a second conductivity type arranged between the first source region and the first semiconductor region, and
the second transistor further includes a second semiconductor region of the first conductivity type arranged away from the second source region, and a second well region of the second conductivity type arranged between the second source region and the second semiconductor region, the first drain region adjoining the first semiconductor region while distant from the first well region, and having a higher impurity concentration than the impurity concentration of the first semiconductor region, and the second drain region adjoining the second semiconductor region while distant from the second well region, and having a higher impurity concentration than does the second semiconductor region.
3. The semiconductor device according to claim 1 , wherein the control element is arranged to straddle a boundary between the first region and the second region.
4. The semiconductor device according to claim 1 , wherein the semiconductor element further includes at least one electrode pad configured to connect to the control element, the at least one electrode pad being arranged on the one surface side of the semiconductor element, and in a planar view from a normal direction of the semiconductor substrate, the control element is arranged between the drain electrode pad or the source electrode pad and the at least one electrode pad.
5. The semiconductor device according to claim 4 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element,
the first transistor further includes a first semiconductor region of the first conductivity type arranged away from the first source region, and a first well region of a second conductivity type arranged between the first source region and the first semiconductor region,
the second transistor further includes a second semiconductor region of the first conductivity type arranged away from the second source region, and a second well region of the second conductivity type arranged between the second source region and the second semiconductor region, and
the semiconductor element includes, as the at least one electrode pad, a first gate electrode pad electrically connected to a first gate electrode of the first transistor and a second gate electrode pad electrically connected to a second gate electrode of the second transistor,
the first gate electrode pad is electrically connected to the first gate electrode formed via a first gate insulating film on a front surface of the first well region between the first source region and the first semiconductor region of the first transistor, and
the second gate electrode pad is electrically connected to the second gate electrode formed via a second gate insulating film on a front surface of the second well region between the second source region and the second semiconductor region of the second transistor, and the first gate electrode pad and the second gate electrode pad are arranged at an outer peripheral portion of the semiconductor substrate.
6. The semiconductor device according to claim 5 , wherein the first gate electrode is embedded, via the first gate insulating film, in a first trench formed from the one surface side of the semiconductor element, and the second gate electrode is embedded, via the second gate insulating film, in a second trench formed from the one surface side of the semiconductor element.
7. The semiconductor device according to claim 4 , wherein the semiconductor element includes, as the at least one electrode pad, a current detecting electrode pad configured to detect current flowing through the semiconductor substrate, and the current detecting electrode pad is electrically connected to a part of the first source region or the second source region and arranged at the outer peripheral portion of the semiconductor substrate.
8. The semiconductor device according to claim 4 , wherein the semiconductor element includes, as the at least one electrode pad, a potential detecting electrode pad configured to detect potential of the semiconductor substrate, and the potential detecting electrode pad is electrically connected to a part of the first source region or the second source region and arranged at the outer peripheral portion of the semiconductor substrate.
9. The semiconductor device according to claim 1 , further comprising a package configured to cover the semiconductor element and the control element.
10. The semiconductor device according to claim 2 , wherein
the first transistor includes a first resurf region of the second conductivity type arranged between the first well region and a boundary between the first region and the second region, the first resurf region having a depth from a front surface of the first semiconductor region which is greater than a depth of the first well region from the front surface of the first semiconductor region,
the second transistor includes a second resurf region of the second conductivity type arranged between the second well region and the boundary between the first region and the second region, the second resurf region having a depth from a front surface of the second semiconductor region which is greater than a depth of the second well region from the front surface of the second semiconductor region.
11. The semiconductor device according to claim 2 , wherein
the control element is arranged to straddle a boundary between the first region and the second region.
12. The semiconductor device according to claim 2 , wherein
the control element is arranged to straddle a boundary between the first region and the second region, and
a channel stopper region of the second conductivity type is provided at the boundary, spaced apart from each of the first well region and the second well region, and having a same depth as the first well region from a front surface of the first semiconductor region and a same depth as the second well region from a front surface of the second semiconductor region.
13. The semiconductor device according to claim 1 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element, and
the second source region is of the first conductivity type and arranged on the one surface side of the semiconductor element.
14. The semiconductor device according to claim 3 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element, and
the second source region is of the first conductivity type and arranged on the one surface side of the semiconductor element.
15. The semiconductor device according to claim 4 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element, and
the second source region is of the first conductivity type and arranged on the one surface side of the semiconductor element.
16. The semiconductor device according to claim 9 , wherein
the first source region is of a first conductivity type and arranged on the one surface side of the semiconductor element, and
the second source region is of the first conductivity type and arranged on the one surface side of the semiconductor element.
17. The semiconductor device according to claim 5 , wherein the semiconductor element includes, as the at least one electrode pad, a current detecting electrode pad configured to detect current flowing through the semiconductor substrate, and the current detecting electrode pad is electrically connected to a part of the first source region or the second source region and arranged at the outer peripheral portion of the semiconductor substrate.
18. The semiconductor device according to claim 6 , wherein the semiconductor element includes, as the at least one electrode pad, a current detecting electrode pad configured to detect current flowing through the semiconductor substrate, and the current detecting electrode pad is electrically connected to a part of the first source region or the second source region and arranged at the outer peripheral portion of the semiconductor substrate.
19. A semiconductor device, comprising:
a control element; and
a semiconductor element, including:
a semiconductor substrate including a first region and a second region adjacent to each other,
a first transistor, provided in the first region, having a first source region and a first drain region,
a second transistor, provided in the second region, having a second source region and a second drain region, the second drain region of the second transistor being connected to and integrated with the first drain region of the first transistor,
a drain electrode pad provided in the first region and arranged on one surface side of the semiconductor element, the drain electrode pad being electrically connected to the first source region of the first transistor,
a source electrode pad provided in the second region and arranged on the one surface side of the semiconductor element, the source electrode pad being arranged away from the drain electrode pad and being electrically connected to the second source region of the second transistor, and
at least one electrode pad configured to connect to the control element, the at least one electrode pad being arranged on the one surface side of the semiconductor element,
wherein
the control element is arranged on the one surface side of the semiconductor element and configured to turn on and off the first transistor and the second transistor, and
in a planar view from a normal direction of the semiconductor substrate, the control element is arranged between the drain electrode pad or the source electrode pad and the at least one electrode pad.