Independent set data lanes for IOD SSD

1. A method for providing a solid-state drive (SSD), comprising:

enabling, by a controller of the SSD, a plurality of data lanes for communicating messages for a plurality of regions of a non-volatile memory, each of the plurality of regions comprising a plurality of dies;

identifying a plurality of processors within the controller of the SSD, wherein enabling includes configuring each one of the plurality of data lanes to communicate respective ones of the messages between each of the plurality of processors within the controller, and further configuring the each one of the plurality of data lanes to communicate the respective ones of the messages between at least one of the plurality of processors and the non-volatile memory, and wherein the each one of the plurality of data lanes is configured to communicate the respective ones of the messages independently and separately from all of the other data lanes; and

communicating, by the controller, the messages for the plurality of regions via the plurality of data lanes.

2. The method of claim 1 , wherein

the non-volatile memory is an array of non-volatile memory dies or an array of NAND flash memory devices;

each of the non-volatile memory dies has at least one plane;

two or more of the non-volatile memory dies are coupled to a same channel of a plurality of channels; and

each of the plurality of regions comprises some of the non-volatile memory dies coupled to at least one of the plurality of channels.

3. The method of claim 1 , further comprising determining whether to enable one of the data lanes for communicating the respective ones of the messages for a corresponding one of each of the plurality of regions or to enable the one data lane for communicating the respective ones of the messages for all of the plurality of regions.

4. The method of claim 3 , further comprising, in response to enabling the one data lane for communicating the respective ones of the messages for all of the plurality of regions, communicating the respective ones of the messages for the plurality of regions via the data lane.

5. The method of claim 1 , wherein each of the plurality of data lanes is operatively coupled to a corresponding one of the plurality of regions.

6. The method of claim 5 , wherein communicating the messages for the plurality of regions via the data lanes comprises communicating all messages for each of the plurality of regions via a corresponding one of the plurality of data lanes.

7. The method of claim 1 , wherein the data lanes are enabled by configuring firmware of the controller.

8. The method of claim 1 , wherein enabling the data lanes is performed during a first power-on sequence of the SSD.

9. The method of claim 1 , wherein enabling the data lanes comprises:

determining a number of data lanes to be enabled; and

enabling the data lanes based on the number.

10. The method of claim 9 , wherein each of the plurality of regions is a non-volatile memory (NVM) set.

11. The method of claim 1 , wherein

each data lane comprises at least one inter-process communication (IPC); and

the at least one IPC corresponds to a communication link between two processors of the controller.

12. The method of claim 11 , wherein each of the at least one IPC comprises a software queue.

13. The method of claim 11 , wherein each of the at least one IPC comprises a physical IPC port.

14. The method of claim 1 , wherein each of the messages for each of the plurality of regions comprises a region identifier that identifies one of the plurality of regions for which each of the messages is communicated.

15. The method of claim 1 , wherein enabling the data lanes for communicating the messages for the plurality of regions comprises:

enabling a plurality of inter-process communications (IPCs) between a sender processor of the controller and a receiver processor of the controller, each of the plurality of IPCs corresponds to a different one of the plurality of regions; and

determining a depth of each of the plurality of IPCs based on a processing capability of the receiver processor and a total number of the plurality of regions.

16. A Solid State Drive (SSD), comprising:

a non-volatile memory having a plurality of regions, each of the plurality of regions comprising a plurality of dies; and

a controller configured to:

enable a plurality of data lanes for communicating messages for the plurality of regions;

identify a plurality of processors within the controller, wherein enabling includes configuring each one of the plurality of data lanes to communicate respective ones of the messages between the plurality of processors of the controller, and further configuring the each one of the plurality of data lanes to communicate the respective ones of the messages between at least one of the plurality of processors and the non-volatile memory, and wherein the each one of the plurality of data lanes is configured to communicate the respective ones of the messages independently and separately from all of the other data lanes; and

communicate the messages for the plurality of regions via the plurality of data lanes.

17. The SSD of claim 16 , wherein the controller is further configured to determine whether to enable one of the data lanes for communicating the respective ones of the messages for a corresponding one of the plurality of regions or to enable the one data lane for communicating the respective ones of the messages for all of the plurality of regions.

18. The SSD of claim 16 , wherein

the plurality of data lanes are operatively coupled to the plurality of regions;

each of the plurality of data lanes is operatively coupled to a corresponding one of the plurality of regions; and

communicating the messages for the plurality of regions via the data lanes comprises communicating all messages for each of the plurality of regions via a corresponding one of the plurality of data lanes.

19. The SSD of claim 16 , wherein

each of the data lanes comprises at least one inter-process communication (IPC);

each of the at least one IPC corresponds to a communication link between two processors of the controller; and

each of the at least one IPC comprises a software queue or a physical IPC port.

20. A non-transitory computer-readable medium storing computer-readable instructions, such that when executed, causes a controller of a Solid State Drive (SSD) to:

enable a plurality of data lanes for communicating messages for a plurality of regions of a non-volatile memory, each of the plurality of regions comprising a plurality of dies;

identify a plurality of processors within the controller, wherein enabling includes configuring each one of the plurality of data lanes to communicate respective ones of the messages between the plurality of processors of the controller, and further configuring the each one of the plurality of data lanes to communicate the respective ones of the messages between at least one of the plurality of processors and the non-volatile memory, and wherein the each one of the plurality of data lanes is configured to communicate the respective ones of the messages independently and separately from all of the other data lanes; and

communicate the messages for the plurality of regions via the data lanes.