High speed interconnect symbol stream forward error-correction
Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.
1. At least one machine-readable storage medium comprising instructions, that when executed by circuitry, cause the circuitry to:
receive a block comprising a plurality of symbols, the block based on a high-speed interconnect symbol stream;
generate at least one forward-error correction (FEC) parity symbol based in part on the plurality of symbols of the block; and
generate an information element from the block and the at least one FEC parity symbol.
2. The at least one machine-readable storage medium of claim 1 , comprising instructions, that when executed by the circuitry, cause the circuitry to:
receive the high-speed interconnect symbol stream; and
split the high-speed interconnect symbol stream into a plurality of blocks comprising k symbols, where the block is one of the plurality of blocks, and where k is an integer greater than two.
3. The at least one machine-readable storage medium of claim 2 , comprising instructions, that when executed by the circuitry, cause the circuitry to generate y FEC parity symbols, where y is an integer greater than two.
4. The at least one machine-readable storage medium of claim 3 , wherein k is 250.
5. The at least one machine-readable storage medium of claim 4 , wherein y is 4.
6. The at least one machine-readable storage medium of claim 5 , comprising instructions, that when executed by the circuitry, cause the circuitry to generate the y FEC parity symbols based in part on a Reed Solomon (RS) (n, k) error-correction code, where n equals y plus k.
7. The at least one machine-readable storage medium of claim 6 , wherein the RS (n, k) error-correction code based on a Galois Fields (GF) of 2 m .
8. The at least one machine-readable storage medium of claim 6 , wherein the plurality of symbols of the block comprise 8b10b encoded line link (LL) symbols.
9. The at least one machine-readable storage medium of claim 1 , comprising instructions, that when executed by the circuitry, cause the circuitry to transmit the information element, comprising the block and the at least one FEC symbol, to a receiver via the high-speed interconnect.
10. The at least one machine-readable storage medium of claim 1 , wherein the high-speed interconnect is a DisplayPort interconnect.
11. An apparatus, comprising:
circuitry, the circuitry arranged to:
receive a block comprising a plurality of symbols;
generate at least one forward-error correction (FEC) parity symbol based in part on the plurality of symbols of the block; and
generate an information element from the block and the at least one FEC parity symbol.
12. The apparatus of claim 11 , the circuitry arranged to:
receive a high-speed interconnect symbol stream; and
split the high-speed interconnect symbol stream into a plurality of blocks comprising k symbols, where the block is one of the plurality of blocks, and where k is an integer greater than two.
13. The apparatus of claim 12 , the circuitry arranged to generate y FEC parity symbols, where y is an integer greater than two.
14. The apparatus of claim 13 , wherein k is 250 and y is 4.
15. The apparatus of claim 14 , the circuitry arranged to generate the y FEC parity symbols based in part on a Reed Solomon (RS) (n, k) error-correction code, where n equals y plus k.
16. The apparatus of claim 15 , wherein the RS (n, k) error-correction code based on a Galois Fields (GF) of 2 m .
17. The apparatus of claim 11 , wherein the plurality of symbols of the block comprise 8b10b encoded line link (LL) symbols.
18. The apparatus of claim 11 , comprising a high-speed interconnect, the circuitry arranged to transmit the information element, comprising the block and the at least one FEC symbol, to a receiver via the high-speed interconnect.
19. The apparatus of claim 18 , wherein the high-speed interconnect is a DisplayPort interconnect.
20. An apparatus, comprising:
a high-speed interconnect; and
circuitry, the circuitry arranged to:
receive an information element via the high-speed interconnect, the information element comprising an indication of a block comprising a plurality of symbols and at least one forward-error correction (FEC) parity symbol,
identify the at least one FEC parity symbol from the information element, and
detect one or more errors in the block based on the at least one FEC parity symbol.
21. The apparatus of claim 20 , wherein the block comprises k symbols and the information element comprises an indication of y FEC parity symbols, where k and y are integers greater than 2.
22. The apparatus of claim 21 , wherein k is 250 and y is 4.
23. The apparatus of claim 22 , wherein the y FEC parity symbols are based in part on the block and a Reed Solomon (RS) (n, k) error-correction code, where n equals y plus k.
24. The apparatus of claim 23 , wherein the RS (n, k) error-correction code based on a Galois Fields (GF) of 2 m .
25. The apparatus of claim 20 , wherein the plurality of symbols of the block comprise 8b10b encoded line link (LL) symbols.
26. The apparatus of claim 20 , wherein the high-speed interconnect is a DisplayPort interconnect.
27. A method, comprising:
receiving an information element via a high-speed interconnect, the information element comprising an indication of a block comprising a plurality of symbols and at least one forward-error correction (FEC) parity symbol;
identifying the at least one FEC parity symbol from the information element; and
detecting one or more errors in the block based on the at least one FEC parity symbol.
28. The method of claim 27 , wherein the block comprises k symbols and the information element comprises an indication of y FEC parity symbols, where k and y are integers greater than 2.
29. The method of claim 28 , wherein k is 250 and y is 4.
30. The method of claim 29 , wherein the y FEC parity symbols are based in part on the block and a Reed Solomon (RS) (n, k) error-correction code, where n equals y plus k.
31. The method of claim 30 , wherein the RS (n, k) error-correction code based on a Galois Fields (GF) of 2 m .
32. The method of claim 27 , wherein the plurality of symbols of the block comprise 8b10b encoded line link (LL) symbols.
33. The method of claim 27 , wherein the high-speed interconnect is a DisplayPort interconnect.