System for integration of elemental and compound semiconductors on a ceramic substrate
A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
1. A semiconductor structure comprising:
an engineered substrate comprising:
a polycrystalline substrate;
a first adhesion layer encapsulating the polycrystalline substrate;
a conductive layer encapsulating the first adhesion layer; and
a second adhesion layer encapsulating the conductive layer;
a barrier layer encapsulating the second adhesion layer; and
a bonding layer coupled to the barrier layer; and
a semiconductor layer coupled to the engineered substrate, the semiconductor layer comprising:
two or more silicon regions disposed on the bonding layer, each of the two or more silicon regions comprising a single crystalline silicon layer and having a surface in a first crystalline orientation, wherein adjacent silicon regions are separated from each other; and
one or more compound semiconductor regions, each of the one or more compound semiconductor regions being disposed on the bonding layer and between adjacent silicon regions.
2. The semiconductor structure of claim 1 wherein the polycrystalline substrate comprises polycrystalline aluminum gallium nitride (AlGaN).
3. The semiconductor structure of claim 1 wherein each of the one or more compound semiconductor regions comprises a III-V semiconductor.
4. The semiconductor structure of claim 3 wherein each of the one or more compound semiconductor regions comprises GaAs.
5. The semiconductor structure of claim 3 further comprising one or more gallium nitride (GaN) based devices coupled to the one or more silicon regions, and one or more III-V based devices coupled to the one or more compound semiconductor regions.
6. The semiconductor structure of claim 1 wherein the first crystalline orientation is ( 111 ) orientation of silicon.
7. The semiconductor structure of claim 1 wherein each of the first adhesion layer and the second adhesion layer comprises tetraethyl orthosilicate (TEOS).
8. The semiconductor structure of claim 1 wherein the conductive layer comprises polysilicon.
9. The semiconductor structure of claim 1 wherein the barrier layer comprises silicon nitride.
10. The semiconductor structure of claim 1 wherein the bonding layer comprises an electrically insulating material.
11. The semiconductor structure of claim 1 wherein the bonding layer comprises silicon oxide.
12. The semiconductor structure of claim 1 wherein each of the one or more compound semiconductor regions is disposed directly on the bonding layer.