Inner spacers for gate-all-around semiconductor devices

1. A semiconductor device, comprising:

a substrate comprising a first p-type well and a second p-type well;

a first shallow trench isolation (STI) feature extending into the substrate, a portion of the first STI feature being disposed over the first p-type well;

a second STI feature extending into the substrate, a portion of the second STI feature being disposed over the second p-type well;

a first gate-all-around (GAA) transistor disposed directly over the first p-type well, the first GAA transistor comprising a first plurality of channel members extending along a first direction and a first gate structure wrapping around each of the first plurality of channel members, the first gate structure comprising a first gate dielectric layer over the first plurality of channel members and a first gate electrode extending along a second direction perpendicular to the first direction;

a second GAA transistor disposed directly over the second p-type well, the second GAA transistor comprising a second plurality of channel members extending along the first direction and a second gate structure wrapping around each of the second plurality of channel members, the second gate structure comprising a second gate dielectric layer over the second plurality of channel members and a second gate electrode extending along the second direction; and

a hard mask layer disposed on the first gate structure and the second gate structure,

wherein the first plurality of channel members has a first pitch (P 1 ) and the second plurality of channel members has a second pitch (P 2 ) smaller than the first pitch (P 1 ),

wherein the first gate structure is disposed between two first gate end dielectric features along the second direction,

wherein the two first gate end dielectric features are disposed directly on the first STI feature,

wherein the second gate structure is disposed between two second gate end dielectric features along the second direction,

wherein the two second gate end dielectric features are disposed directly on the second STI features,

wherein the first gate structure is in physical contact with the first p-type-well and the second gate structure is in physical contact with the second p-type well,

wherein the hard mask layer is disposed on top surfaces of the two first gate end dielectric features, the two second gate end dielectric features, the first gate structure, and the second gate structure.

2. The semiconductor device of claim 1 ,

wherein the first gate dielectric layer comprises a first thickness (G 1 ) and the second gate dielectric layer comprises a second thickness (G 2 ) smaller than the first thickness (G 1 ).

3. The semiconductor device of claim 2 , wherein a ratio of the first thickness to the second thickness (G 1 /G 2 ) is between about 1.3 and about 3.0.

4. The semiconductor device of claim 1 , wherein a ratio of the first pitch to the second pitch (P 1 /P 2 ) is between about 1.05 and about 1.3.

5. The semiconductor device of claim 1 ,

wherein the first plurality of channel members includes a first spacing (S 1 ) between two neighboring channel members of the first plurality of channel members,

wherein the second plurality of channel members includes a second spacing (S 2 ) between two neighboring channel members of the second plurality of channel members,

wherein the first spacing (S 1 ) is greater than the second spacing (S 2 ).

6. The semiconductor device of claim 5 , wherein a ratio of the first spacing to the second spacing (S 1 /S 2 ) is between about 1.05 and about 1.4.

7. The semiconductor device of claim 1 ,

wherein each of the first plurality of channel members comprises a first channel thickness (T 1 ),

wherein each of the second plurality of channel members comprises a second channel thickness (T 2 ),

wherein a ratio of the first channel thickness to the second channel thickness (T 1 /T 2 ) is between about 0.9 and about 1.3.

8. The semiconductor device of claim 1 ,

wherein each of the first plurality of channel members comprises a first number (N1) of channel members,

wherein each of the second plurality of channel members comprises a second number (N2) of channel members,

wherein the first number (N1) is smaller than the second number (N2).

9. The semiconductor device of claim 1 , further comprising:

a third GAA transistor comprising a third plurality of channel members extending the first direction; and

a fourth GAA transistor comprising a fourth plurality of channel members extending along the first direction,

wherein the substrate further comprises a first n-type well adjacent the first p-type well and a second n-type well adjacent the second p-type well,

wherein the third GAA transistor is disposed over the first n-type well and the fourth GAA transistor is disposed over the second n-type well,

wherein the first gate electrode wraps around each of the third plurality of channel members,

wherein the second gate electrode wraps around each of the fourth plurality of channel members.

10. A semiconductor device, comprising:

an input/output (I/O) region comprising a first gate-all-around (GAA) transistor that includes:

a first plurality of channel members disposed over a first doped well and extending from a first source/drain feature to a second source/drain feature along a direction,

a first gate structure wrapping around each of the first plurality of channel members, and

a dielectric gate structure; and

a core region comprising a second GAA transistor that includes:

a second plurality of channel members disposed over a second doped well, and

a second gate structure wrapping around each of the second plurality of channel members,

wherein the first plurality of channel members has a first pitch (P 1 ) and the second plurality of channel members has a second pitch (P 2 ) smaller than the first pitch (P 1 ),

wherein the first source/drain feature is disposed between the first gate structure and the dielectric gate structure along the direction,

wherein the first gate structure is in physical contact with the first doped well and the second gate structure is in physical contact with the second doped well.

11. The semiconductor device of claim 10 , wherein a ratio of the first pitch to the second pitch (P 1 /P 2 ) is between about 1.05 and about 1.3.

12. The semiconductor device of claim 10 ,

wherein the first GAA transistor further includes a first gate dielectric layer over the first plurality of channel members,

wherein the second GAA transistor further includes a second gate dielectric layer over the second plurality of channel members,

wherein the first gate dielectric layer comprises a first thickness (G 1 ) and the second gate dielectric layer comprises a second thickness (G 2 ) smaller than the first thickness (G 1 ).

13. The semiconductor device of claim 10 ,

wherein each of the first plurality of channel members comprises a first gate length (GL1),

wherein each of the second plurality of channel members comprises a second gate length (GL2),

wherein a ratio of the first gate length to the second gate length (GL1/GL2) is greater than 2.

14. The semiconductor device of claim 10 ,

wherein each of the first plurality of channel members comprises a first number (N1) of channel members,

wherein each of the second plurality of channel members comprises a second number (N2) of channel members,

wherein the first number (N1) is smaller than the second number (N2).

15. A semiconductor structure, comprising:

a substrate including a first n-type well and a second n-type well;

first channel members directly over the first n-type well, the first channel members being vertically stacked one over another and extending along a first direction;

a first gate structure wrapping around each of the first channel members and extending along a second direction perpendicular to the first direction;

second channel members directly over the second n-type well, the second channel members being vertically stacked one over another and extending along the first direction; and

a second gate structure wrapping around each of the second channel members and extending along the second direction,

wherein a number of the first channel members is smaller than a number of the second channel members,

wherein the first gate structure is disposed between two first gate end dielectric features along the second direction,

wherein the second gate structure is disposed between two second gate end dielectric features along the second direction,

wherein the first gate structure is in physical contact with the first n-type well and the second gate structure is in physical contact with the second n-type well.

16. The semiconductor structure of claim 15 , wherein the first channel members comprise a first pitch (P 1 ) and the second channel members comprise a second pitch (P 2 ) smaller than the first pitch (P 1 ).

17. The semiconductor structure of claim 16 , wherein a ratio of the first pitch to the second pitch (P 1 /P 2 ) is between about 1.05 and about 1.3.

18. The semiconductor structure of claim 15 ,

wherein the first gate structure comprises a first gate dielectric layer,

wherein the second gate structure comprises a second gate dielectric layer,

wherein the first gate dielectric layer comprises a first thickness (G 1 ) and the second gate dielectric layer comprises a second thickness (G 2 ) smaller than the first thickness (G 1 ).

19. The semiconductor structure of claim 15 ,

wherein the first channel members comprise a first gate length (GL1), and

wherein the second channel members comprise a second gate length (GL2) smaller than the first gate length (GL1).

20. The semiconductor structure of claim 19 ,

wherein a ratio of the first gate length to the second gate length (GL1/GL2) is greater than 2.