Method of filling gaps with carbon and nitrogen doped film

1. A method comprising:

etching a semiconductor substrate to form a trench;

depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle, wherein the dielectric layer extends into the trench, and wherein the ALD cycle comprises:

pulsing Hexachlorodisilane (HCD) to the semiconductor substrate;

purging the HCD;

pulsing triethylamine to the semiconductor substrate; and

purging the triethylamine; and

performing an anneal process on the dielectric layer, wherein the anneal process comprises:

a first wet anneal process performed at a first temperature;

a second wet anneal process performed at a second temperature higher than the first temperature; and

a dry anneal process performed at a third temperature higher than the first temperature.

2. The method of claim 1 , wherein the ALD cycle further comprises:

after the triethylamine is purged, pulsing oxygen (O 2 ) to the semiconductor substrate; and

purging the oxygen.

3. The method of claim 2 further comprising repeating the ALD cycle that comprising the pulsing oxygen.

4. The method of claim 1 further comprising repeating the ALD cycle.

5. The method of claim 1 , wherein the first wet anneal process is performed at the first temperature in a range between about 300° C. and about 450° C.

6. The method of claim 1 , wherein the second wet anneal process is performed at the second temperature in a range between about 500° C. and about 650° C.

7. The method of claim 1 , wherein the dry anneal process is performed at the third temperature in a range between about 500° C. and about 650° C.

8. The method of claim 1 , wherein the etching the semiconductor substrate further generates a wide trench, and the trench is a narrow trench narrower than the wide trench, and at a time the anneal process is performed, the narrow trench is fully filled, and the wide trench is partially filled, and a portion of the dielectric layer in the wide trench is conformal.

9. A method comprising:

depositing a dielectric layer on a semiconductor strip, wherein the depositing the dielectric layer comprises a cycle, and the cycle comprises:

attaching silicon and chlorine atoms to oxygen atoms on the semiconductor strip;

replacing the chlorine atoms with nitrogen atoms and alkyl groups; and

replacing first portions of the nitrogen atoms and alkyl groups with oxygen atoms;

removing second portions of the nitrogen atoms and alkyl groups with OH bonds; and

annealing the dielectric layer to form Si—O—Si bonds, wherein the annealing the dielectric layer comprises:

driving H 2 O molecules into the dielectric layer at a first temperature;

replacing the nitrogen atoms and alkyl groups with oxygen atoms and OH molecules at a second temperature higher than the first temperature; and

forming the Si—O—Si bonds through a dry anneal process, wherein the dry anneal process is performed at a third temperature higher than the first temperature.

10. The method of claim 9 , wherein the cycle comprises an Atomic Layer Deposition (ALD) cycle, and the attaching silicon and chlorine atoms comprises:

pulsing Hexachlorodisilane (HCD); and

purging the HCD.

11. The method of claim 9 , wherein the cycle comprises an Atomic Layer Deposition (ALD) cycle, and the replacing the chlorine atoms comprises:

pulsing triethylamine; and

purging the triethylamine.

12. The method of claim 9 , wherein the cycle comprises an Atomic Layer Deposition (ALD) cycle, and the replacing the first portions of the nitrogen atoms and alkyl groups comprises:

pulsing oxygen (O 2 ); and

purging the oxygen.

13. The method of claim 9 , wherein the dielectric layer is formed in a trench, with the semiconductor strip being on a side of the trench, and the method further comprises:

forming an additional dielectric region, wherein the semiconductor strip and the additional dielectric region contact opposite sidewalls of a portion of the dielectric layer;

etching back the portion of the dielectric layer, wherein a top portion of the semiconductor strip forms a semiconductor fin, and a top portion of the additional dielectric region forms a dummy dielectric fin; and

forming a gate stack extending on the semiconductor fin and the additional dielectric region.

14. The method of claim 9 , wherein the dielectric layer extends into a narrow trench and a wide trench in the semiconductor substrate, and wherein at a time the annealing the dielectric layer is performed, the narrow trench is fully filled, and the wide trench is partially filled, and a portion of the dielectric layer in the wide trench is conformal.

15. A method comprising:

forming a first semiconductor strip;

depositing a dielectric layer comprising silicon oxide, with carbon doped in the silicon oxide, wherein the dielectric layer comprises:

a horizontal portion; and

a vertical portion connected to an end of the horizontal portion, wherein the vertical portion contacts a sidewall of a lower portion of the first semiconductor strip, wherein a top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin; and

forming a gate stack extending on a sidewall and a top surface of the semiconductor fin.

16. The method claim 15 further comprising:

forming a dielectric region overlapping the horizontal portion, wherein a top portion of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin, wherein the gate stack further extends on a sidewall and a top surface of the dummy dielectric fin.

17. The method of claim 16 , wherein the dielectric region and the dielectric layer are formed of different dielectric materials.

18. The method of claim 16 further comprising depositing an inter-layer dielectric overlapping the dummy dielectric fin.

19. The method of claim 15 , wherein the dielectric layer is deposited using a conformal deposition process.

20. The method of claim 15 further comprising, after the depositing the dielectric layer and before the forming the gate stack:

performing a first wet anneal process at a first temperature;

after the first wet anneal process, performing a second wet anneal process at a second temperature higher than the first temperature; and

after the second wet anneal process, performing a dry anneal process performed at a third temperature higher than the first temperature.