Offset voltage trimming for operational amplifiers

1. An operational amplifier comprising:

a first differential pair of pMOS transistors, the first differential pair biased by a first bias current that has a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, a ratio of the first and second portions generating a first transconductance of the first differential pair that is substantially constant for temperatures over a range;

a second differential pair of nMOS transistors, the second differential pair biased by a second bias current that has a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, a ratio of the first and second portions generating a second transconductance of the second differential pair that is substantially constant for temperatures over the range; and

a comparator that activates either the first differential pair or the second differential pair based on an input voltage at an input.

2. The operational amplifier according to claim 1 , wherein the comparator couples the input to the first differential pair when the input voltage is less than a reference voltage, and wherein the comparator couples the input to the second differential pair when the input voltage is greater than the reference voltage.

3. The operational amplifier according to claim 1 , further comprising:

a first trimming circuit that includes a first current source generating a first trim current, the first trimming circuit configurable to trim the first bias current through one of the pMOS transistors in the first differential pair of pMOS transistors to correct a first voltage offset of the first differential pair; and

a second trimming circuit that includes a second current source generating a second trim current, the second trimming circuit configurable to trim the second bias current through one of the nMOS transistors in the second differential pair of nMOS transistors to correct a second voltage offset of the second differential.

4. The operational amplifier according to claim 3 , wherein the first voltage offset and the second voltage offset are adjusted by the first trim current and the second trim current, respectively, to approximately zero volts at approximately 25 degrees Celsius.

5. The operational amplifier according to claim 3 , wherein

the first trim current is constant with temperature to provide a first voltage offset that has a first temperature coefficient that is substantially the same before and after the trimming; and

the second trim current is constant with temperature to provide a second voltage offset that has a second temperature coefficient that is substantially the same before and after the trimming.

6. The operational amplifier according to claim 1 , wherein:

the second portion of the first bias current that is proportional to absolute temperature is subtracted from an output of the first differential pair so that only the first portion that is constant with temperature is transmitted to subsequent stages in the operational amplifier; and

the second portion of the second bias current that is proportional to absolute temperature is subtracted from an output of the second differential pair so that only the first portion that is constant with temperature is transmitted to subsequent stages in the operational amplifier.

7. The operational amplifier according to claim 1 , wherein:

the first differential pair of pMOS transistors are operated in a subthreshold region; and

the second differential pair of nMOS transistors are operated in a subthreshold region.

8. A method for reducing an offset voltage in an operational amplifier, the method comprising:

applying a first bias current to a first differential pair of transistors, the first bias current including a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, a ratio of the first and second portions selected so that a first transconductance of the first differential pair is substantially constant for temperatures over a range;

generating a first trim current to trim the first bias current through one of the transistors in the first differential pair to reduce a first voltage offset of the first differential pair of transistors towards zero volts;

applying a second bias current to a second differential pair of transistors, the second bias current including a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, the ratio of the first and second portions selected so that a second transconductance of the second differential pair is substantially constant for temperatures over a range; and

generating a second trim current to trim the second bias current through one of the transistors in the second differential pair of transistors to reduce a second voltage offset of the second differential pair of transistors towards zero volts.

9. The method for reducing an offset voltage in an operational amplifier according to claim 8 , wherein

the first differential pair of transistors includes pMOS transistors; and

the second differential pair of transistors includes nMOS transistors.

10. The method for reducing an offset voltage in an operational amplifier according to claim 8 , further comprising:

activating, based on an input voltage at an input, either the first differential pair of transistors or the second differential pair of transistors; and

coupling the input to the activated differential pair of transistors.

11. The method for reducing an offset voltage in an operational amplifier according to claim 8 , wherein:

the first voltage offset has a first temperature coefficient that is substantially unaffected by the trimming of the first bias current; and

the second voltage offset has a second temperature coefficient that is substantially unaffected by the trimming of the second bias current.

12. The method for reducing an offset voltage in an operational amplifier according to claim 8 , further comprising:

subtracting, from an output of the first differential pair, the second portion of the first bias current that is proportional to absolute temperature so that only the first portion that is constant with temperature is transmitted to subsequent stages in the operational amplifier; and

subtracting, from an output of the second differential pair, the second portion of the second bias current that is proportional to absolute temperature so that only the first portion that is constant with temperature is transmitted to subsequent stages in the operational amplifier.

13. The method for reducing an offset voltage in an operational amplifier according to claim 8 , further comprising:

operating the first differential pair transistors in a subthreshold region; and

operating the second differential pair transistors in a subthreshold region.

14. A rail-to-rail operational amplifier comprising:

a first differential pair of p-type transistors configured to be biased by a first bias current, the first bias current having a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, an amount of the second portion selected so that a first transconductance of the first differential pair is substantially constant over a range of temperature;

a first trimming circuit that is coupled to the first differential pair of p-type transistors and that is configured to trim the first bias current through one of the p-type transistors in the pair of p-type transistors to adjust a first offset voltage towards zero volts;

a second differential pair of n-type transistors configured to be biased by a second bias current, the second bias current having a first portion that is constant with temperature and a second portion that is proportional to absolute temperature, an amount of the second portion selected so that a second transconductance of the second differential pair is substantially constant over a range of temperature; and

a second trimming circuit that is coupled to the second differential pair of n-type transistors and that is configured to trim the second bias current through one of the n-type transistors in the pair of n-type transistors to adjust a second offset voltage towards zero volts.

15. The rail-to-rail operational amplifier according to claim 14 , further comprising a bias control circuit that includes comparators configured to control (i) the first bias current to activate the first differential pair or (ii) the second bias current to activate the second different pair, the control based on a comparison of an input common mode voltage to a threshold voltage.

16. The rail-to-rail operational amplifier according to claim 15 , wherein:

the first trimming circuit is configured to adjust the first offset voltage using a first trim current that is constant over temperature so that a first temperature coefficient of the first voltage offset is unaffected by the trimming; and

the second trimming circuit is configured to adjust the second offset voltage using a second trim current that is constant over temperature so that a second temperature coefficient of the second voltage offset is unaffected by the trimming.

17. The rail-to-rail operational amplifier according to claim 16 , wherein:

the first trimming circuit is activated simultaneously with the first differential pair by the bias control circuit; and

the second trimming circuit is activated simultaneously with the second differential pair by the bias control circuit.

18. The rail-to-rail operational amplifier according to claim 16 , wherein the first offset voltage and the second offset voltage are approximately the same after trimming.

19. The rail-to-rail operational amplifier according to claim 14 , wherein:

the p-type transistors are pMOS transistors operated in a subthreshold region; and the n-type transistors are nMOS transistors operated in a subthreshold region.