Securing microprocessors against information leakage and physical tampering
A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.
1. A system comprising:
machine storage storing a compiler that is executable to compile a computer program to produce executable instructions, the executable instructions comprising:
a first zone comprised of first instructions having a first type of encoding;
a second zone comprised of second instructions having a second type of encoding, the first type of encoding being different from the second type of encoding; and
an instruction that is outside of the second zone, the instruction comprising a payload; and
microarchitecture to execute the executable instructions, wherein executing the executable instructions comprises using first control information to decode the first instructions and using second control information to decode the second instructions, the second control information being based on the payload;
wherein at least one of (i) the first control information is discarded after the first control information is used to decode the first instructions or (ii) the second control information is discarded after the second control information is used to decode the second instructions.
2. The system of claim 1 , wherein the second zone follows the first zone in the executable instructions.
3. The system of claim 1 , wherein the instruction is between the first zone and the second zone.
4. The system of claim 1 , wherein the instruction is at a boundary between the first zone and the second zone.
5. The system of claim 1 , wherein the instruction is in the first zone.
6. The system of claim 1 , wherein at least one of the first zone or the second zone comprises a branch instruction having a target address defined in another zone contained within the executable instructions.
7. The system of claim 1 , wherein the microarchitecture is configured to switch on one or more arithmetic and logic units in the microarchitecture when an instruction being executed does not use the one or more arithmetic and logic units.
8. The system of claim 1 , wherein the system is part of a process device; and
wherein the microarchitecture is configured to replace operations with software interrupts during executing the executable instructions in order to change a power profile of the processing device.
9. The system of claim 1 , wherein the executable instructions comprise multiple zones including the first zone and the second zone, each of the multiple zones having a different type of encoding; and
wherein all instructions included in the executable instructions are part of one of the multiple zones.
10. The system of claim 1 , wherein the executable instructions comprise multiple zones including the first zone and the second zone, each of the multiple zones having a different type of encoding; and
wherein some instructions included in the executable instructions are not part of one of the multiple zones.
11. The system of claim 1 , wherein the payload is memory-mapped to a register in the first zone.
12. The system of claim 1 , wherein the payload is loadable from the first zone in correlation with a time-specific event that is external to the system.
13. The system of claim 1 , wherein the payload is loadable from the first zone in correlation with a time-specific event that is internal to the system.
14. The system of claim 1 , wherein the payload comprises a mutation to produce the second instructions having the second type of encoding.
15. The system of claim 1 , wherein the first zone, the second zone, and the instruction comprise components of an instruction set architecture, the complier to compile the computer program to produce the instruction set architecture at compile-time.
16. The system of claim 15 , wherein the instruction set architecture is unique to a device configured to execute the executable instructions.
17. The system of claim 1 , further comprising:
a programmable device that is programmable to execute the executable instructions.
18. The system of claim 1 , wherein the microarchitecture is configured to produce an encoding scheme for the executable instructions during first power-on of a device comprising the system by randomly modifying the payload and rewriting one or more of the executable instructions based on the modified payload.
19. A system comprising:
non-transitory machine-readable storage storing a compiler to generate a binary comprising executable instructions for execution by a processing device, the compiler to perform operations comprising:
generating a first zone of the binary, the first zone comprising first instructions having a first type of encoding;
generating a second zone of the binary, the second zone comprising second instructions having a second type of encoding, the first type of encoding being different from the second type of encoding; and
generating an instruction that is outside of the second zone, the instruction comprising a payload; and
microarchitecture to use first control information to decode the first instructions and to use second control information to decode the second instructions, the second control information being based on the payload;
wherein at least one of (i) the first control information is discarded after the first control information is used to decode the first instructions or (ii) the second control information is discarded after the second control information is used to decode the second instructions.
20. The system of claim 19 , wherein the second zone follows the first zone in the executable instructions.
21. The system of claim 19 , wherein the instruction is between the first zone and the second zone.
22. The system of claim 19 , wherein the instruction is at a boundary between the first zone and the second zone.
23. The system of claim 19 , wherein the instruction is in the first zone.
24. The system of claim 19 , wherein at least one of the first zone or the second zone comprises a branch instruction having a target address defined in another zone contained within the binary.
25. The system of claim 19 , wherein the binary comprises multiple zones including the first zone and the second zone, each of the multiple zones having a different type of encoding; and
wherein all instructions included in the executable instructions are part of one of the multiple zones.
26. The system of claim 19 , wherein the binary comprises multiple zones including the first zone and the second zone, each of the multiple zones having a different type of encoding; and
wherein some instructions included in the executable instructions are not part of one of the multiple zones.
27. The system of claim 19 , wherein the payload is memory-mapped to a register in the first zone.
28. The system of claim 19 , wherein the payload is loadable from the first zone in correlation with a time-specific event that is external to the processing device.
29. The system of claim 19 , wherein the payload is loadable from the first zone in correlation with a time-specific event that is internal to the processing device.
30. The system of claim 19 , wherein the payload comprises a mutation to produce the second instructions having the second type of encoding, the mutation being viable for a limited time.
31. The system of claim 19 , wherein the first zone, the second zone, and the instruction comprise components of an instruction set architecture, the complier to compile a computer program to produce the instruction set architecture at compile-time.
32. The system of claim 31 , wherein the instruction set architecture is unique to a device that comprises the system.
33. The system of claim 19 that is part of a programmable device.