Process-induced distortion prediction and feedforward and feedback correction of overlay errors
Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
1. A method, comprising:
acquiring shape and thickness maps of a wafer before and after the wafer is processed by a wafer process tool;
calculating shape and thickness difference maps based on the shape and thickness maps of the wafer acquired before and after the wafer is processed by the wafer process tool;
extracting slope of shape change residue and curvature of wafer shape change from the shape and thickness difference maps of the wafer;
calculating an overlay error induced by the wafer process tool at least partially based on: the slope and the curvature from the shape and thickness difference maps; and
adjusting one or more process tools of a semiconductor fabrication facility based on the calculated overlay error.
2. The method of claim 1 , wherein the curvature includes curvature of wafer shape change in an X direction CSC x and curvature of wafer shape change in a Y direction CSC y .
3. The method of claim 2 , wherein the overlay error induced by the wafer process tool in X direction and the overlay error induced by the wafer process tool in Y direction are calculated based on:
slope of shape change residue in the X direction SSCR x ;
slope of shape change residue in the Y direction SSCR y ;
the curvature of wafer shape change in the X direction CSC x ;
the curvature of wafer shape change in the Y direction CSC y ; and
a second order shape change residue component SOSCR.
4. The method of claim 3 , wherein the overlay error induced by the wafer process tool in the X direction and the overlay error induced by the wafer process tool in the Y direction are calculated as:
OverlayError x =a xx SSCR x +a xy SSCR y +b xx CSC x +b xy CSC y +c xx SOSCR
OverlayError y =a yx SSCR x +a yy SSCR y +b yx CSC y +b yy CSC y +c yy SOSCR
wherein coefficients a xx to c yy are weighting coefficients.
5. The method of claim 4 , wherein at least some of the coefficients a xx to c yy are constant weighting coefficients.
6. The method of claim 4 , wherein at least some of the coefficients a xx to c yy are variable weighting coefficients.
7. The method of claim 4 , further comprising:
using at least one of wafer thickness spatial variations or thickness differences at a spatial position to enhance the overlay error prediction.
8. The method of claim 1 , further comprising:
adjusting the wafer process tool based on the calculated overlay error induced by the wafer process tool.
9. The method of claim 8 , wherein the adjusting the wafer process tool based on the calculated overlay error is iteratively adjusted until a difference between the calculated overlay error and a measured overlay error is below a predetermined threshold.
10. A system, comprising:
a geometry measurement tool configured to acquire shape and thickness maps of a wafer before and after the wafer is processed by a wafer process tool; and
a processor configured to:
calculate shape and thickness difference maps based on the shape and thickness maps of the wafer acquired before and after the wafer is processed by the wafer process tool;
extract slope of shape change residue and curvature of wafer shape change from the shape and thickness difference maps of the wafer;
calculate an overlay error induced by the wafer process tool at least partially based on: the slope and the curvature from the shape and thickness difference maps; and
adjust one or more process tools of a semiconductor fabrication facility based on the calculated overlay error.
11. The system of claim 10 , wherein the curvature includes curvature of wafer shape change in an X direction CSC x and curvature of wafer shape change in a Y direction CSC y .
12. The system of claim 11 , wherein the overlay error induced by the wafer process tool in X direction and the overlay error induced by the wafer process tool in Y direction are calculated by the processor based on:
slope of shape change residue in the X direction SSCR x ;
slope of shape change residue in the Y direction SSCR y ;
the curvature of wafer shape change in the X direction CSC x ;
the curvature of wafer shape change in the Y direction CSC y ; and
a second order shape change residue component SOSCR.
13. The system of claim 12 , wherein the overlay error induced by the wafer process tool in the X direction and the overlay error induced by the wafer process tool in the Y direction are calculated as:
OverlayError x =a xx SSCR x +a xy SSCR y +b xx CSC x +b xy CSC y +c xx SOSCR
OverlayError y =a yx SSCR x +a yy SSCR y +b yx CSC x +b yy CSC y +c yy SOSCR
wherein coefficients a xx to c yy are weighting coefficients.
14. The system of claim 13 , wherein at least some of the coefficients a xx to c yy are constant weighting coefficients.
15. The system of claim 13 , wherein at least some of the coefficients a xx to c yy are variable weighting coefficients.
16. A system, comprising:
a processor, the processor configured to:
receive shape and thickness maps of a wafer from a geometry measurement tool before and after the wafer is processed by a wafer process tool;
calculate shape and thickness difference maps based on the shape and thickness maps of the wafer acquired before and after the wafer is processed by the wafer process tool;
extract slope of shape change residue and curvature of wafer shape change from the shape and thickness difference maps of the wafer;
calculate an overlay error induced by the wafer process tool at least partially based on: the slope and the curvature from the shape and thickness difference maps; and
adjust one or more process tools of a semiconductor fabrication facility based on the calculated overlay error.
17. The system of claim 16 , wherein the curvature includes curvature of wafer shape change in an X direction CSC x and curvature of wafer shape change in a Y direction CSC y .
18. The system of claim 17 , wherein the overlay error induced by the wafer process tool in the X direction and the overlay error induced by the wafer process tool in the Y direction are calculated by the processor based on:
slope of shape change residue in the X direction SSCR x ;
slope of shape change residue in the Y direction SSCR y ;
the curvature of wafer shape change in the X direction CSC x ;
the curvature of wafer shape change in the Y direction CSC y ; and
a second order shape change residue component SOSCR.
19. The system of claim 18 , wherein the overlay error induced by the wafer process tool in the X direction and the overlay error induced by the wafer process tool in the Y direction are calculated as:
OverlayError x =a xx SSCR x +a xy SSCR y +b xx CSC x +b xy CSC y +c xx SOSCR
OverlayError y =a yx SSCR x +a yy SSCR y +b yx CSC x +b yy CSC y +c yy SOSCR
wherein coefficients a xx to c yy are weighting coefficients.
20. The system of claim 19 , wherein the coefficients a xx to c yy are either constant or variable weighting coefficients.