Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.
1. A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs), the method comprising:
forming a stack comprising vertically-alternating insulative tiers and conductive tiers, the stack comprising a TAV region and an operative memory-cell-string region, the TAV region comprising spaced operative TAV areas;
forming operative channel-material strings in the stack in the operative memory-cell-string region and forming dummy channel-material strings in the stack in the TAV region laterally outside of and not within the operative TAV areas; and
forming operative TAVs in individual of the spaced operative TAV areas in the TAV region.
2. The method of claim 1 comprising forming the operative and dummy channel-material strings at the same time.
3. The method of claim 1 comprising forming the operative TAVs after forming the operative and dummy channel-material strings.
4. The method of claim 1 comprising forming the operative and dummy channel-material strings to individually have the same horizontal shape relative one another.
5. The method of claim 1 comprising forming the operative and dummy channel-material strings to individually have the same size and shape relative one another.
6. The method of claim 1 comprising forming the operative channel-material strings and the dummy channel-material strings to have the same pitch relative one another.
7. The method of claim 6 comprising forming the operative and dummy channel-material strings to individually have the same size and shape relative one another.
8. The method of claim 1 comprising forming the operative and dummy channel-material strings to individually be horizontally smaller than the operative TAVs.
9. The method of claim 1 wherein the operative channel-material strings are within laterally-spaced memory blocks that comprise part of a memory plane; the dummy channel-material strings, the TAV region, and the operative TAVs being within the memory plane.
10. The method of claim 1 wherein the operative channel-material strings are within laterally-spaced memory blocks that comprise part of a memory plane; the dummy channel-material strings, the TAV region, and the operative TAVs being outside of the memory plane.
11. The method of claim 10 wherein the dummy channel-material strings, the TAV region, and the operative TAVs are edge-of-plane.
12. The method of claim 10 ,
wherein the dummy channel-material strings, the TAV region, and the operative TAVs are formed in a landing region of a stair-step region; and
further comprising:
forming an operative stair-step structure into the stack in the stair-step region and a landing in the landing region of the stair-step region.
13. The method of claim 12 wherein the landing is a crest of the operative stair-step structure.
14. The method of claim 1 wherein the operative channel-material strings are within laterally-spaced memory blocks that comprise part of a memory plane; and
further comprising:
forming multiple of said TAV regions that are laterally spaced relative one another, at least one of said TAV regions being within the memory plane, at least another one of said TAV regions being outside of the memory plane.
15. The method of claim 1 comprising forming CMOS-under-array circuitry.
16. The method of claim 1 wherein the operative TAVs directly electrically couple digitlines of the memory array with CMOS-under-array circuitry.
17. The method of claim 1 comprising forming the memory array to comprise NAND.
18. The method of claim 1 comprising:
forming individual memory cells of the strings of memory cells to comprise channel material of the operative channel-material strings, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material of the operative channel-material strings in the individual conductive tiers; and
forming conducting material of the conductive lines after forming the operative and dummy channel-material strings.
19. The method of claim 1 comprising:
forming individual memory cells of the strings of memory cells to comprise channel material of the operative channel-material strings, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material of the operative channel-material strings in the individual conductive tiers; and
forming conducting material of the conductive lines before forming the operative and dummy channel-material strings.