IP Library › Granted Patent US 11,145,764
Granted Patent B2
US 11,145,764 · App. 16/532,791 · Granted Oct 12, 2021

Display device

Inventor: Hidekazu Miyake (Minato-ku, JP)
Assignee: Japan Display Inc.
H01L29/78648H01L27/124H01L27/1225H01L29/4175H01L29/41733H01L29/7869G02F1/1368G02F1/136286H01L27/3262H01L27/3276
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,145,764
App. No.
16/532,791
Granted
Oct 12, 2021
Kind
B2
Abstract

A display device includes a pixel layer for displaying an image and a circuit layer including a thin film transistor for driving the pixel layer. The thin film transistor includes a semiconductor layer including a channel region and a source region and a drain region sandwiching the channel region, a first gate electrode facing the channel region on a first side which is either above or below the semiconductor layer, a second gate electrode facing at least the channel region and the source region on a second side opposite to the first side, a source electrode connected to the source region, and a drain electrode connected to the drain region. The source electrode penetrates through the semiconductor layer and is connected to the second gate electrode on the second side.

Claims (48)

1. A display device comprising:

a pixel layer for displaying an image; and

a circuit layer including a thin film transistor for driving the pixel layer, wherein

the thin film transistor includes

a semiconductor layer including a channel region and a source region and a drain region sandwiching the channel region,

a first gate electrode facing the channel region on a first side which is either on or below the semiconductor layer,

a second gate electrode facing at least the channel region and the source region on a second side opposite to the first side,

a source electrode connected to the source region, and

a drain electrode connected to the drain region, and

the source electrode penetrates through the semiconductor layer and is connected to the second gate electrode on the second side, wherein

the drain electrode penetrates through the semiconductor layer and extends to the second side without contacting the second gate electrode,

the second gate electrode has a central region overlapping with the first gate electrode each other, and has a first end below a side of the drain electrode and a second end below a side of the source electrode,

a distance from the central region to the second end is larger than a distance from the first gate electrode to the source electrode in a plan view,

the first end and the second end are equally spaced apart from the central region,

the second gate electrode faces the drain region and has a hole, and

the drain electrode extends inside the hole of the second gate electrode.

2. The display device according to claim 1 , wherein

a distance from the central region to the first end is smaller than a distance from the first gate electrode to the drain electrode in a plan view.

3. The display device according to claim 1 , wherein

the drain electrode is farther away from the first gate electrode than the source electrode in a plan view.

4. The display device according to claim 1 , wherein

the source electrode and the drain electrode are equally spaced from the first gate electrode.

5. The display device according to claim 1 , wherein

the thin film transistor is a first thin film transistor,

the semiconductor layer is a first semiconductor layer,

the circuit layer further includes a second thin film transistor, and

the second thin film transistor includes a second semiconductor layer farther away from the first semiconductor layer than the first gate electrode, on the first side.

6. The display device according to claim 5 , wherein

at least one of the source electrode and the drain electrode penetrates through the second semiconductor layer and is shared by the first thin film transistor and the second thin film transistor.

7. The display device according to claim 6 , wherein

the second thin film transistor shares one of the source electrode and the drain electrode with the first thin film transistor, and further includes one of a second source electrode and a second drain electrode.

8. The display device according to claim 7 , wherein

the second semiconductor layer has a first portion extending in a first direction from the one of the source electrode and the drain electrode, and a second portion extending in a second direction intersecting the first direction,

the one of the source electrode and the drain electrode penetrates through the first portion, and

the one of the second source electrode and the second drain electrode penetrates through the second portion.

9. The display device according to claim 7 , wherein

the circuit layer further includes a wiring having a portion, which is in contact with and mounted on the second semiconductor layer, in connection with one of the second source electrode and the second drain electrode, on the first side.

10. The display device according to claim 5 , wherein

the circuit layer further includes a source wiring connected to the source electrode and a drain wiring connected to the drain electrode, on the first side, and

at least one of the source wiring and the drain wiring has a portion which is in contact with and mounted on the second semiconductor layer.

11. The display device according to claim 5 , wherein

the second semiconductor layer overlaps the first semiconductor layer, and

the first thin film transistor and the second thin film transistor share the first gate electrode.

12. The display device according to claim 5 , wherein

the second thin film transistor includes a third gate electrode, and

the third gate electrode and the first gate electrode are same layers.

13. The display device according to claim 5 , wherein

the second semiconductor layer is made of an oxide semiconductor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2019
From: MIYAKE, HIDEKAZU
To: JAPAN DISPLAY INC.
Reel/Frame 049970/0822 →
Priority Claims (1)
JP JP2018-150623 · Aug 9, 2018 · national
Continuity (1)
Related Publication 20200052129A1 · Feb 13, 2020