System and method for controlling the impact of process and temperature in passive signal detector for automotive ethernet

1. A system for process and temperature compensated passive signal detection, the system comprising:

a voltage level detector;

a first transistor with a drain electrically connected to a first input of the voltage level detector, the first transistor having a threshold voltage of a first voltage value, wherein a threshold voltage corresponds to a minimum gate-to-source voltage to create a conducting path between source and drain terminals of a transistor; and

a second transistor with a drain electrically connected to a second input of the voltage level detector, the second transistor having a threshold voltage of the first voltage value, wherein

an offset voltage is applied across a gate of the first transistor and a source of the second transistor,

the offset voltage is applied across a gate of the second transistor and a source of the first transistor,

a difference between a threshold voltage of the first voltage value and the offset voltage is constant, and

the offset voltage is produced using a third transistor and a fourth transistor each having a threshold voltage of the first voltage value, a supply voltage, and a plurality of resistors.

2. The system of claim 1 , wherein the offset voltage is produced across a drain of the third transistor and a source of the fourth transistor.

3. The system of claim 2 , wherein the drain of the third transistor is connected to a gate of the third transistor.

4. The system of claim 2 , wherein the drain of the fourth transistor is connected to a gate of the fourth transistor.

5. The system of claim 1 , wherein the plurality of resistors comprises a first pair of resistors each with resistance of a first resistance value, a second pair of resistors each with resistance of a second resistance value, and a third pair of resistors each with resistance of a third resistance value.

6. The system of claim 1 , wherein the offset voltage is configured to be process and temperature dependent.

7. A method for performing process and temperature compensated passive signal detection, the method comprising:

electrically connecting a drain of a first transistor to a first input of a voltage level detector, the first transistor having a threshold voltage of a first voltage value, wherein a threshold voltage corresponds to a minimum gate-to-source voltage to create a conducting path between source and drain terminals of a transistor;

electrically connecting a drain of a second transistor to a second input of the voltage level detector, the second transistor having a threshold voltage of the first voltage value;

applying an offset voltage across a gate of the first transistor and a source of the second transistor; and

applying the offset voltage across a gate of the second transistor and a source of the first transistor, wherein

a difference between a threshold voltage of the first voltage value and the offset voltage is constant, and

the method further comprises producing the offset voltage using a third transistor and a fourth transistor each having a threshold voltage of the first voltage value, a supply voltage, and a plurality of resistors.

8. The method of claim 7 , comprising producing the offset voltage across a drain of the third transistor and a source of the fourth transistor.

9. The method of claim 8 , further comprising connecting the drain of the third transistor to a gate of the third transistor.

10. The method of claim 8 , further comprising connecting the drain of the fourth transistor to a gate of the fourth transistor.

11. The method of claim 7 , wherein the plurality of resistors comprises a first pair of resistors each with resistance of a first resistance value, a second pair of resistors each with resistance of a second resistance value, and a third pair of resistors each with resistance of a third resistance value.

12. The method of claim 7 , wherein the offset voltage is configured to be process and temperature dependent.

13. Circuitry comprising:

voltage level detector circuitry configured to detect a voltage level;

a first transistor with a drain electrically connected to a first input of the voltage level detector circuitry, the first transistor having a threshold voltage of a first voltage value, wherein a threshold voltage corresponds to a minimum gate-to-source voltage to create a conducting path between source and drain terminals of a transistor; and

a second transistor with a drain electrically connected to a second input of the voltage level detector circuitry, the second transistor having a threshold voltage of the first voltage value, wherein

an offset voltage is applied across a gate of the first transistor and a source of the second transistor,

the offset voltage is applied across a gate of the second transistor and a source of the first transistor,

a difference between a threshold voltage of the first voltage value and the offset voltage is constant, and

the offset voltage is produced using a third transistor and a fourth transistor each having a threshold voltage of the first voltage value, a supply voltage, and a plurality of resistors.

14. The circuitry of claim 13 , wherein the offset voltage is produced across a drain of the third transistor and a source of the fourth transistor.

15. The circuitry of claim 14 , wherein the drain of the third transistor is connected to a gate of the third transistor.

16. The circuitry of claim 15 , wherein the drain of the fourth transistor is connected to a gate of the fourth transistor.

17. The circuitry of claim 13 , wherein the plurality of resistors comprises a first pair of resistors each with resistance of a first resistance value, a second pair of resistors each with resistance of a second resistance value, and a third pair of resistors each with resistance of a third resistance value.