IP Library › Granted Patent US 11,016,846
Granted Patent B2
US 11,016,846 · App. 16/533,894 · Granted May 25, 2021

Storage device using host memory and operating method thereof

Inventors: Kicheol Eom (Seoul, KR); Jaeho Sim (Seoul, KR); Dong-Ryoul Lee (Incheon, KR); Hyun Ju Yi (Hwseong-si, KR); Hyotaek Leem (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F11/1068G06F3/0619G06F3/0656G06F3/0659G06F3/0679G06F13/1668G06F13/28G06F13/4282
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Quick Facts
Patent No.
US 11,016,846
App. No.
16/533,894
Filed
Aug 7, 2019
Granted
May 25, 2021
Kind
B2
Art Unit
2112
USPC
714/764
Abstract

A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.

Claims (36)

1. A storage device sharing a host memory of a host, comprising:

a serial interface configured to exchange data with the host;

a storage controller connected to the host through the serial interface, and configured to store buffering data in a host memory buffer allocated by the host and to perform error correction encoding and error correction decoding on the buffering data; and

a nonvolatile memory device provided as a storage medium,

wherein the storage controller comprises

a first error correction code engine configured to perform the error correction encoding and error correction decoding on the buffering data, and

a second error correction code engine configured to perform error correction encoding and error correction decoding on storage data exchanged with the nonvolatile memory device.

2. The storage device of claim 1 , wherein the host memory buffer comprises a data region and a parity region.

3. The storage device of claim 1 , wherein the storage controller further comprises a host memory buffer (HMB) controller configured to manage the buffering data exchanged with the host memory buffer.

4. The storage device of claim 3 , wherein the serial interface comprises a direct memory access (DMA) circuit configured to perform a direct memory access with the host memory buffer.

5. The storage device of claim 1 , wherein the storage controller is configured to detect an error of the buffering data, and

when the detected error is correctable, the storage controller is further configured to store error-corrected buffering data in the nonvolatile memory device after correcting the detected error.

6. The storage device of claim 5 , wherein when the detected error is uncorrectable, the storage controller is configured to again read the buffering data from the host memory buffer.

7. The storage device of claim 5 , wherein when the detected error is uncorrectable, the storage controller is configured to notify the host of a read fail of the buffering data.

8. The storage device of claim 7 , wherein the host is configured to reallocate the host memory buffer to another region of the host memory in response to the read fail of the buffering data.

9. The storage device of claim 1 , wherein when a link down state of the serial interface occurs while receiving the buffering data from the host memory buffer, the storage controller is configured to replace a lost packet of the buffering data with dummy data to release a system hang.

10. The storage device of claim 9 , wherein before replacing the lost packet with the dummy data, the storage controller is configured to first restore the lost packet through decoding using the error correction decoding.

11. An operating method of a storage device which is allocated a host memory of a host as a buffer, the method comprising:

reading, at the storage device, buffering data from the buffer;

detecting an error of the buffering data by using a first error correction code engine; and

requesting, by the storage device, the buffering data from the host to perform a read retry operation when the detected error is uncorrectable by the first error correction code engine.

12. The method of claim 11 , further comprising correcting the detected error of the buffering data by using the first error correction engine when the detected error is correctable.

13. The method of claim 12 , further comprising encoding the error-corrected buffering data by using a second error correction engine, and storing the encoded error-corrected buffering data in a storage medium of the storage device.

14. The method of claim 11 , further comprising:

receiving, at the storage device, buffering data to be stored in the buffer;

performing error correction code encoding on the received buffering data by using the first error correction code engine; and

writing the encoded buffering data in the buffer.

15. A storage device comprising:

an interface configured to exchange data with a host;

a nonvolatile memory device; and

a storage controller connected to the interface, and configured to store buffering data in a partial region of a host memory of the host allocated as a buffer, to control the nonvolatile memory device responsive to the buffering data, and to perform error correction encoding and error correction decoding on the buffering data,

wherein the storage controller is further configured to replace a lost portion of a packet of the buffering data that is lost when an error occurs at the interface during receiving of the buffering data, wherein the lost portion is replaced with dummy data.

16. The storage device of claim 15 , wherein the storage controller is configured to restore the lost portion of the packet by using the error correction encoding on a received portion of the packet when the error occurs.

17. The storage device of claim 15 , wherein the interface enters a hang state when the error occurs, and the storage controller is configured to release the hang state of the interface by using a packet which is obtained by replacing the lost portion of the packet with the dummy data.

18. The storage device of claim 17 , wherein the storage controller is configured to notify the host of a receive fail of the buffering data after releasing the hang state.

19. The storage device of claim 15 , wherein the storage controller is configured to process the packet restored to include the lost portion replaced with the dummy data as invalid data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2019
From: EOM, KICHEOL; SIM, JAEHO; LEE, DONG-RYOUL; YI, HYUN JU; LEEM, HYOTAEK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 050020/0170 →
Priority Claims (1)
KR 10-2018-0137228 · Nov 9, 2018 · national
Continuity (1)
Related Publication 20200151055A1 · May 14, 2020
Cited By (2)
US 12,271,605 US 12,299,321