Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure, exposing the upper structure to a plasma treatment, and exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process.
1. A method for fabricating a semiconductor device, the method comprising:
forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure;
exposing the upper structure to a plasma treatment; and
exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process,
wherein the plasma protection layer includes a non-conductive segment that partially covers the top electrode, and the plasma treatment is focused on the segment.
2. The method of claim 1 , wherein the plasma protection layer is formed of a material having a high etch selectivity with respect to the plasma treatment.
3. The method of claim 1 , wherein the plasma protection layer is formed of a material having a high hydrogen diffusivity with respect to the hydrogen passivation process.
4. The method of claim 1 , wherein the plasma treatment is focused on the plasma protection layer.
5. The method of claim 1 , wherein the plasma treatment includes an etch process using plasma.
6. The method of claim 1 , wherein the exposing of the upper structure to the plasma treatment includes:
forming an interlayer dielectric layer on the upper structure;
forming one or more contact holes by performing a plasma etch process on the interlayer dielectric layer so that the etch process is stopped at the plasma protection layer; and
etching the plasma protection layer exposed by the contact holes so as to expose the top electrode.
7. The method of claim 6 , wherein the forming of the contact holes by performing the plasma etch process on the interlayer dielectric layer includes:
performing a main etch process to vertically etch the interlayer dielectric layer; and
performing a post-etch process to remove polymers formed during the main etch process.
8. The method of claim 1 , wherein the plasma protection layer includes undoped polysilicon.
9. The method of claim 1 , wherein the upper structure further comprising a supporter that supports the bottom electrode.
10. The method of claim 9 , wherein the plasma protection layer includes a material having engineered stress.
11. The method of claim 1 , wherein the plasma protection layer includes engineered stressed silicon nitride.
12. A method for fabricating a semiconductor device, comprising:
forming a capacitor in which a bottom electrode, a dielectric layer and a top electrode are sequentially stacked on a lower structure;
forming a plasma protection layer including a plurality of non-conductive segments on the top electrode;
forming an interlayer dielectric layer on the plasma protection layer;
forming a contact hole landing on each of the segments by performing a plasma etch process on the interlayer dielectric layer;
partially etching the segments to expose the top electrode below the contact hole;
forming a metal wiring connected to the top electrode through the contact hole; and
exposing the capacitor, the metal wiring and the lower structure to a hydrogen passivation process.
13. The method of claim 12 , wherein the plasma protection layer is formed of a material having a high etch selectivity with respect to the plasma etch process.
14. The method of claim 12 , wherein the plasma protection layer is formed of a material having a high hydrogen diffusivity with respect to the hydrogen passivation process.
15. The method of claim 12 , wherein the plasma etch process is focused on the non-conductive segments.
16. The method of claim 12 , wherein the plasma protection layer includes undoped polysilicon.
17. The method of claim 12 , wherein the plasma protection layer includes engineered stressed silicon nitride.
18. The method of claim 12 , wherein the forming of the capacitor further includes forming a supporter that supports the bottom electrode.
19. The method of claim 12 , wherein the forming of the contact hole includes:
performing a main etch process to vertically etch the interlayer dielectric layer; and
performing a post-etch process to remove polymers formed during the main etch process.