IP Library Granted Patent US 10,950,503
Granted Patent B2
US 10,950,503 · App. 16/535,562 · Granted Mar 16, 2021

Method of separating electronic devices having a back layer and apparatus

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Quick Facts
Patent No.
US 10,950,503
App. No.
16/535,562
Granted
Mar 16, 2021
Kind
B2
Abstract

A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed along the second major surface. The method includes placing the wafer onto a carrier substrate. The method includes singulating the wafer through the spaces to form singulation lines after the placing the wafer on the carrier substrate, wherein singulating comprises stopping in proximity to the layer of material. The method includes applying a pressure to the entire wafer thereby separating the layer of material in the singulation lines, wherein applying the pressure comprises using a fluid. The method provide a way to batch separate layers of material disposed on wafers after singulating the wafers.

Claims (52)

1. A method of singulating a wafer comprising:

providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has a first major surface and a second major surface opposite to the first major surface, and wherein a layer of material is formed over the second major surface;

placing the wafer onto a carrier substrate;

singulating the wafer through the spaces to form singulation lines after the step of placing the wafer on the carrier substrate without singulating through the layer of material so that portions of the layer of material extend to overlap the singulation lines; and

applying a pressure to the entire layer of material thereby separating the portions of the layer of material that extend to overlap the singulation lines, wherein applying the pressure comprises using a fluid.

2. The method of claim 1 , wherein applying the pressure comprises applying the pressure through the carrier substrate.

3. The method of claim 1 , wherein:

applying the pressure comprises:

placing the wafer and carrier substrate within a chamber, the chamber at least partially enclosing a pressure transfer vessel, wherein the pressure transfer vessel contains the fluid; and

moving a compression structure against the pressure transfer vessel thereby applying the pressure substantially uniformly along the second major surface to separate the portions of the layer of material.

4. The method of claim 3 , wherein:

placing the wafer and the carrier substrate within the chamber comprises placing the pressure transfer vessel against the carrier substrate so that the carrier substrate is between the pressure transfer vessel and the wafer; and wherein the pressure transfer vessel has a width that exceeds that of the wafer.

5. The method of claim 4 further comprising:

placing a pressure plate between the pressure transfer vessel and the carrier substrate.

6. The method of claim 1 , wherein:

providing the wafer comprises providing a semiconductor wafer where the layer of material comprises a conductive material.

7. The method of claim 1 further comprising placing a protective film proximate to the first major surface of the wafer before applying the pressure.

8. The method of claim 1 , wherein applying the pressure comprises extruding portions of the carrier substrate into the singulation lines to separate the portions of the layer of material.

9. The method of claim 1 , further comprising heating at least one of the wafer or the carrier substrate during at least a portion of the step of applying the pressure.

10. A method of singulating a layer of material on a singulated semiconductor substrate comprising:

providing a semiconductor substrate that is attached to a carrier substrate, the semiconductor substrate having a plurality of die formed as part of the semiconductor substrate and separated from each other by singulation lines comprising gaps, wherein the semiconductor substrate has a first major surface and a second major surface opposite to the first major surface, and wherein the layer of material is disposed atop the second major surface, and wherein the singulation lines terminate without extending through to the layer of material so that portions of the layer of material overlap the singulation lines; and

separating the portions of the layer of material that overlap the singulation lines using a fluid to apply a pressure to the entire layer of material.

11. The method of claim 10 , wherein separating comprises:

placing the semiconductor substrate and the carrier substrate within a chamber, the chamber at least partially enclosing a pressure transfer vessel that contains the fluid; and

applying a pressure to the pressure transfer vessel thereby applying a transferred pressure to the entire layer of material.

12. A method for batch singulating a semiconductor wafer comprising:

providing the semiconductor wafer comprising:

a plurality of die separated from each other by spaces,

a first major surface,

a second major surface opposite to the first major surface, and

a layer of material fixed to the second major surface;

placing the semiconductor wafer onto a carrier substrate, wherein the layer of material is adjacent the carrier substrate;

after placing the semiconductor wafer onto the carrier substrate, removing portions the semiconductor wafer through the spaces to form singulation lines comprising gaps and to expose portions of the layer of material that overlap the singulation lines; and

separating the exposed portions of the layer of material that overlap the singulation lines by simultaneously applying a pressure to all of the exposed portions with a fluid.

13. The method of claim 12 , wherein separating comprises applying the pressure through the carrier substrate.

14. The method of claim 12 , further comprising applying heat to at least one of the semiconductor wafer or the carrier substrate during at least a portion of the step of separating.

15. The method of claim 12 , wherein:

providing the semiconductor wafer comprises providing the layer of material comprising a conductive layer.

16. The method of claim 12 , wherein:

providing the semiconductor wafer comprises providing the layer of material comprising a wafer back coat film.

17. The method of claim 12 , wherein:

providing the semiconductor wafer comprises providing the layer of material comprising a die-attach film.

18. The method of claim 12 , wherein:

separating comprises restraining the semiconductor wafer proximate to the first major surface while applying the pressure.

19. A method for separating a layer of material on a wafer, comprising:

providing the wafer comprising a plurality of electronic die formed as part of the wafer and separated from each other by singulation lines, wherein:

the wafer has a first major surface and a second major surface opposite to the first major surface,

a layer of material atop the second major surface,

the singulation lines extend from the first major surface into the wafer and terminate proximate to the layer of material so that portions of the layer of material overlap the singulation lines, and

the wafer is attached to a carrier substrate; and

separating the portions of the layer of material that overlap the singulation lines using a fluid to apply a pressure to the entire layer of material.

20. The method of claim 19 , wherein providing the wafer comprises providing the layer of material comprising one or more of a conductive layer having a thickness greater than about two microns, a wafer back coat film, or a die attach film.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 051145, FRAME 0062 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0474 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXCLUSION OF FAIRCHILD SEMICONDUCTOR CORPORATION OF CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 051145 FRAME 0062. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Dec 3, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051170/0781 →
SECURITY INTEREST Recorded Nov 26, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051145/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2019
From: GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 050001/0620 →