HIGHLY EFFICIENT MICRODEVICES
Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.
1 . A vertical device comprising:
a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars; and
a first passivation layer formed on a space between the plurality of the nano-pillars and at least a part of sidewalls of the plurality of nano-pillars.
2 . The vertical device of claim 1 , further comprising:
a gate electrode formed on part of the first passivation layer covering the space between the nano-pillars and the sidewalls of the nano-pillars.
3 . The vertical device of claim 2 , wherein a biasing is provided to the plurality of the nano-pillars through the gate electrode to control a charge accumulated on a surface of the plurality of nano-pillars or a current passing through the plurality of nano-pillars.
4 . The vertical device of claim 1 , further comprising:
a second passivation layer formed over the gate electrode; and
a device electrode formed over the second passivation layer to create a functional area for the vertical device, wherein the device electrode comprises one of: a filler layer or a reflector.
5 . The vertical device of claim 1 , further comprising:
an ohmic contact layer formed on a top surface of at least one nano-pillar to create nano-contacts.
6 . The vertical device of claim 4 , wherein the device electrode comprises a separate electrode or a part of nano-contacts.
7 . The vertical device of claim 1 , wherein the plurality of the nano-pillars are etched down to the plurality of planar active layers formed on the substrate.
8 . The vertical device of claim 1 , wherein a surface treatment is provided to the first passivation layer to expose defective areas underneath the nano-pillars and remove the nano-pillars placed on the defective areas.
9 . The vertical device of claim 1 , wherein a surface treatment is provided to the space between the nano-pillars or the sidewalls of the nano-pillars prior to the formation of the first passivation layer to expose defective areas using a chemical etch or a dry plasma etch process.
10 . The vertical device of claim 1 , wherein the nano-pillars on top of defective areas are at least partially deactivated to eliminate the nano-pillars on top of the defective areas.
11 . The vertical device of claim 1 , wherein a surface of the active planar layers is investigated to map the defective areas and a defect map is used to control the formation of nano-pillars on the defective areas by adjusting a position of the nano-pillars.
12 . The vertical device of claim 1 , wherein a size and a density of the plurality of nano-pillars is adjusted based on an operation range of the vertical device and a peak efficiency of the vertical device.
13 . The vertical device of claim 1 , wherein a part of the nano-pillar sidewalls is covered by a dielectric layer and a conductive layer forming a vertical transistor in series of the vertical device, wherein the vertical transistor controls current going through the vertical device.
14 . The vertical device of claim 13 , wherein the dielectric layer and the conductive layer are configured to spread to other areas of the vertical device.
15 . The vertical device of claim 1 , further comprising:
a filler layer formed on a top surface of the first passivation layer, the filler layer includes one of: a polymer, a solgel, and a dielectric.
16 . The vertical device of claim 15 , wherein the filler layer further includes a color conversion layer.
17 . A vertical device comprising:
a plurality of planar active layers formed on a donor substrate;
a thin doped layer formed on one of: a top or a bottom surface of the plurality of active layers;
a passivation layer formed to cover at least a part of the thin doped layer; and
a conductive layer coupled to the planar active layers through the areas not covered by the passivation layer.
18 . The vertical device of claim 17 , wherein the conductive layer acts as a gate layer, wherein a gate voltage applied to the gate layer is adjusted to control an area of the vertical device by controlling the spread of the current to the surface of the vertical device.
19 . The vertical device of claim 17 , wherein the passivation layer covers the exposed defects.
20 . The vertical device of claim 17 , further comprising:
performing a bonding process to bond together the donor substrate to a temporary substrate through a bonding layer; and
removing the donor substrate.
21 . A method of fabricating a vertical device comprising:
providing a plurality of planar active layers on a substrate,
forming a plurality of nano-pillars on at least one of a top layer of the plurality of the active layers; and
forming a first passivation layer on a space between the plurality of the nano-pillars and at least a part of sidewalls of the plurality of nano-pillars.
22 . The method of claim 21 , further comprising:
forming a gate electrode on part of the first passivation layer covering the space between the nano-pillars and the sidewalls of the nano-pillars.