IP Library › Granted Patent US 11,114,394
Granted Patent B2
US 11,114,394 · App. 16/536,997 · Granted Sep 7, 2021

Signal routing carrier

Inventors: Lijiang Wang (Chandler, AZ); Jianyong Xie (Chandler, AZ); Sujit Sharan (Chandler, AZ); Robert L. Sankman (Phoenix, AZ)
Assignee: Intel Corporation
H01L23/66H01L21/4853H01L21/4857H01L23/145H01L23/15H01L23/49822H01L23/49838H01L24/16H01P3/088H01P11/003H01L2223/6616H01L2223/6627H01L2223/6638H01L2224/16227H01L2924/19031
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Quick Facts
Patent No.
US 11,114,394
App. No.
16/536,997
Granted
Sep 7, 2021
Kind
B2
Abstract

An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.

Claims (15)

1. An article comprising:

a substrate;

a semiconductor die thereon;

a routing carrier attached to the substrate; and

a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier,

wherein the transmission pathway has a loss of no more than 2.5 dB at a signaling speed of about 50 Gbpa to about 250 Gbps.

2. The article of claim 1 , wherein the routing carrier is attached to a surface of the substrate.

3. The article of claim 1 , wherein the routing carrier is embedded within the substrate.

4. The article of claim 1 , wherein the routing carrier is a high-speed signal routing carrier.

5. The article of claim 1 , wherein the routing carrier comprises a single-ended interface.

6. The article of claim 1 , wherein the substrate comprises a plurality of dielectric layers interspersed with conductive traces.

7. The article of claim 6 , wherein one or more of the conductive traces is electrically connected to the transmission pathway.

8. The article of claim 1 , wherein the routing carrier comprises a ceramic, a glass, a glass ceramic, or an organic substrate.

9. The article of claim 1 , wherein the routing carrier comprises a serializer deserializer (SerDes).

10. The article of claim 1 , wherein the routing carrier comprises a single-ended interface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2019
From: WANG, LIJIANG; XIE, JIANYONG; SHARAN, SUJIT; SANKMAN, ROBERT L
To: INTEL CORPORATION
Reel/Frame 050216/0474 →
Continuity (1)
Related Publication 20210043588A1 · Feb 11, 2021