Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Inventors: Andrew W. Yeoh (Portland, OR); Joseph Steigerwald (Forest Grove, OR); Jinhong Shin (Hillsboro, OR); Vinay Chikarmane (Portland, OR); Christopher P. Auth (Portland, OR)

Assignee: Intel Corporation

H01L29/66545 H01L21/02532 H01L21/02636 H01L21/0337 H01L21/28247 H01L21/28518 H01L21/28568 H01L21/3086 H01L21/31105 H01L21/31144 H01L21/76224 H01L21/76232 H01L21/76801 H01L21/76802 H01L21/76816 H01L21/76834 H01L21/76846 H01L21/76849 H01L21/76877 H01L21/76897 H01L21/823431 H01L21/823481 H01L21/823807 H01L21/823814 H01L21/823821 H01L21/823828 H01L21/823842 H01L21/823857 H01L21/823871 H01L21/823878 H01L23/528 H01L23/5226 H01L23/5283 H01L23/5329 H01L23/53209 H01L23/53238 H01L23/53266 H01L27/0207 H01L27/0886 H01L27/0922 H01L27/0924 H01L27/1104 H01L28/20 H01L28/24 H01L29/0649 H01L29/0653 H01L29/0847 H01L29/165 H01L29/167 H01L29/41783 H01L29/41791 H01L29/516 H01L29/6653 H01L29/6656 H01L29/66636 H01L29/66795 H01L29/66818 H01L29/785 H01L29/7843 H01L29/7845 H01L29/7846 H01L29/7848 H01L29/7851 H01L29/7854 H01L21/0217 H01L21/02164 H01L21/0332 H01L21/76883 H01L21/76885 H01L21/823437 H01L21/823475 H01L24/16 H01L24/32 H01L24/73 H01L29/665 H01L29/7842 H01L29/7853 H01L2224/16227 H01L2224/32225 H01L2224/73204

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Quick Facts

Patent No.: US 10,854,731
App. No.: 16/537,020
Granted: Dec 1, 2020
Kind: B2

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Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Claims (37)

1. An integrated circuit structure, comprising:

a first plurality of conductive interconnect lines and vias in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines and vias comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and

a second plurality of conductive interconnect lines and vias in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the first conductive barrier material is different in composition from the second conductive barrier material, and wherein individual conductive interconnect lines of the first plurality of conductive interconnect lines and vias are along a first direction, and individual conductive interconnect lines of the second plurality of conductive interconnect lines and vias are along a second direction orthogonal to the first direction, and wherein one of the conductive interconnect lines of the second plurality of conductive interconnect lines and vias is directly coupled to one of the conductive interconnect lines of the first plurality of conductive interconnect lines and vias by one of the vias of the second plurality of conductive interconnect lines and vias.

2. The integrated circuit structure of claim 1 , wherein the first conductive barrier material comprises an outer layer distal from the first conductive fill material and an inner layer proximate to the first conductive fill material, the outer layer comprising titanium and nitrogen, and the inner layer comprising tungsten, nitrogen and carbon.

3. The integrated circuit structure of claim 2 , wherein the outer layer has a thickness of approximately 2 nanometers, and the inner layer has a thickness of approximately 0.5 nanometers.

4. The integrated circuit structure of claim 1 , wherein the second conductive barrier material comprises an outer layer distal from the second conductive fill material and an inner layer proximate to the second conductive fill material, the outer layer comprising tantalum, and the inner layer comprising ruthenium.

5. The integrated circuit structure of claim 4 , wherein the outer layer further comprises nitrogen.

6. The integrated circuit structure of claim 1 , wherein individual conductive interconnect lines of the second plurality of conductive interconnect lines and vias comprise a conductive cap layer on a top of the second conductive fill material.

7. The integrated circuit structure of claim 6 , wherein the conductive cap layer is not on a top of the second conductive barrier material.

8. The integrated circuit structure of claim 1 , wherein individual conductive interconnect lines of the first plurality of conductive interconnect lines and vias have a first width, and individual conductive interconnect lines of the second plurality of conductive interconnect lines and vias have a second width greater than the first width.

9. An integrated circuit structure, comprising:

a third plurality of conductive interconnect lines and vias in and spaced apart by a third ILD layer above the second ILD layer, wherein individual ones of the third plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the first conductive barrier material is different in composition from the second conductive barrier material, and wherein individual ones of the third plurality of conductive interconnect lines and vias are along the first direction, and wherein one of the conductive interconnect lines of the third plurality of conductive interconnect lines and vias is directly coupled to one of the conductive interconnect lines of the second plurality of conductive interconnect lines and vias by one of the vias of the third plurality of conductive interconnect lines and vias;

a fourth plurality of conductive interconnect lines and vias in and spaced apart by a fourth ILD layer above the third ILD layer, wherein individual ones of the fourth plurality of conductive interconnect lines and vias comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the fourth plurality of conductive interconnect lines are along the second direction;

a fifth plurality of conductive interconnect lines and vias in and spaced apart by a fifth ILD layer above the fourth ILD layer, wherein individual ones of the fifth plurality of conductive interconnect lines and vias comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the fifth plurality of conductive interconnect lines are along the first direction; and

a sixth plurality of conductive interconnect lines and vias in and spaced apart by a sixth ILD layer above the fifth ILD layer, wherein individual ones of the sixth plurality of conductive interconnect lines and vias comprise the second conductive barrier material along sidewalls and a bottom of the second conductive fill material, and wherein individual ones of the sixth plurality of conductive interconnect lines are along the second direction.

10. The integrated circuit structure of claim 9 , wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt.

11. The integrated circuit structure of claim 9 , wherein the first conductive fill material comprises copper having a first concentration of a dopant impurity atom, and wherein the second conductive fill material comprises copper having a second concentration of the dopant impurity atom, the second concentration of the dopant impurity atom less than the first concentration of the dopant impurity atom.

12. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

13. The computing device of claim 12 , further comprising:

a memory coupled to the board.

14. The computing device of claim 12 , further comprising:

a communication chip coupled to the board.

15. The computing device of claim 12 , further comprising:

a camera coupled to the board.

16. The computing device of claim 12 , further comprising:

a battery coupled to the board.

17. The computing device of claim 12 , further comprising:

an antenna coupled to the board.

18. The computing device of claim 12 , wherein the component is a packaged integrated circuit die.

19. The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. The computing device of claim 12 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Continuity (3)

Continuation 15859416 · Dec 30, 2017

Provisional Application 62593149 · Nov 30, 2017

Related Publication 20200044049A1 · Feb 6, 2020