Granted Patent B2

US 12,362,219 · App. 16/537,564 · Granted Jul 15, 2025

Inventors: Zvi Or-Bach (San Jose, CA); Brian Cronquist (Klamath Falls, OR); Deepak C. Sekar (Sunnyvale, CA); Zeev Wurman (Palo Alto, CA); Israel Beinglass (Sunnyvale, CA)

Assignee: Monolithic 3D Inc.

H01L21/6835G11C8/16H01L21/743H01L21/76254H01L21/76898H01L23/481H01L23/5252H10B10/00H10B10/125H10B12/053H10B12/09H10B12/20H10B12/50H10B20/00H10B20/25H10B41/20H10B41/40H10B41/41H10B43/20H10B43/40H10D10/051H10D30/0411H10D30/0413H10D30/0512H10D30/60H10D30/681H10D30/69H10D30/711H10D30/792H10D64/027H10D64/513H10D84/0172H10D84/038H10D84/85H10D84/907H10D84/998H10D86/01H10D86/201H10D88/00H10D88/01H10D89/10H01L23/3677H01L24/13H01L24/16H01L24/45H01L24/48H01L25/0655H01L25/0657H01L25/50H01L2221/68368H01L2223/5442H01L2223/54426H01L2224/131H01L2224/16145H01L2224/16146H01L2224/16227H01L2224/16235H01L2224/32145H01L2224/32225H01L2224/45124H01L2224/45147H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73253H01L2224/73265H01L2224/81005H01L2224/83894H01L2225/06513H01L2225/06541H01L2924/00011H01L2924/01002H01L2924/01004H01L2924/01013H01L2924/01018H01L2924/01019H01L2924/01029H01L2924/01046H01L2924/01066H01L2924/01068H01L2924/01077H01L2924/01078H01L2924/01322H01L2924/10253H01L2924/10329H01L2924/12032H01L2924/12033H01L2924/12036H01L2924/12042H01L2924/1301H01L2924/1305H01L2924/13062H01L2924/13091H01L2924/14H01L2924/1461H01L2924/15311H01L2924/1579H01L2924/16152H01L2924/181H01L2924/19041H01L2924/30105H01L2924/3011H01L2924/3025H10B12/05H10D86/0214H10D86/40H10D86/60

Abstract

Claims (78)

1. A 3D semiconductor memory, the memory comprising:

a first level comprising first memory cells, first transistors, and a first control line,

wherein said first memory cells each comprise one of said first transistors;

a second level comprising second memory cells, second transistors, and a second control line,

wherein said second memory cells each comprise one of said second transistors,

wherein said second level overlays said first level,

wherein said second control line and said first control line have been processed following the same lithography step and accordingly are self-aligned,

wherein said first control line is directly connected to each source or drain of at least five of said first transistors, and

wherein said second control line is directly connected to each source or drain of at least five of said second transistors; and

an oxide layer disposed between said first control line and said second control line.

2. The 3D semiconductor memory according to claim 1 ,

wherein said second control line comprises silicon.

3. The 3D semiconductor memory according to claim 1 ,

wherein said first transistors each comprise a poly-silicon transistor channel.

4. The 3D semiconductor memory according to claim 1 ,

wherein at least one of said first transistors is self-aligned to at least one of said second transistors, having been processed following the same lithography step.

5. The 3D semiconductor memory according to claim 1 , further comprising:

a plurality of metalized memory control lines; and

a single crystal silicon substrate,

wherein said plurality of memory control lines are primarily disposed between said single crystal silicon substrate and said first level.

6. The 3D semiconductor memory according to claim 1 ,

wherein said first control line comprises silicon.

7. The 3D semiconductor memory according to claim 1 , further comprising:

a single crystal silicon substrate,

wherein said single crystal substrate comprises third transistors, and

wherein at least one of said third transistors is directly below at least a portion of said first transistors.

8. A 3D semiconductor memory, the memory comprising:

a first level comprising first memory cells, first transistors, and a first control line,

wherein said first memory cells each comprise one of said first transistors;

a second level comprising second memory cells, second transistors, and a second control line,

wherein said second memory cells each comprise one of said second transistors,

wherein said second level overlays said first level,

wherein said second control line and said first control line have been processed following the same lithography step and accordingly are self-aligned,

wherein said first control line is directly connected to each source or drain of at least five of said first transistors, and

wherein said second control line is directly connected to each source or drain of at least five of said second transistors; and

an oxide layer disposed between said first control line and said second control line,

wherein said second transistors each comprise a double gate.

9. The 3D semiconductor memory according to claim 8 ,

wherein said second control line comprises silicon.

10. The 3D semiconductor memory according to claim 8 ,

wherein said second transistor comprises a poly-silicon transistor channel.

11. The 3D semiconductor memory according to claim 8 ,

wherein at least one of said first transistors is self-aligned to at least one of said second transistors, having been processed following the same lithography step.

12. The 3D semiconductor memory according to claim 8 , further comprising:

a plurality of metalized memory control lines; and

a single crystal silicon substrate,

wherein said plurality of metalized memory control lines are primarily disposed between said single crystal silicon substrate and said first level.

13. The 3D semiconductor memory according to claim 8 ,

wherein said first control line comprises silicon.

14. The 3D semiconductor memory according to claim 8 , further comprising:

a single crystal silicon substrate,

wherein said single crystal silicon substrate comprises third transistors, and

wherein at least one of said third transistors is disposed directly below at least a portion of said first transistors.

15. A 3D semiconductor memory, the memory comprising:

a first level comprising first memory cells, first transistors, and a first control line,

wherein said first memory cells each comprise one of said first transistors;

a second level comprising second memory cells, second transistors, and a second control line,

wherein said second memory cells each comprise one of said second transistors,

wherein said second level overlays said first level,

wherein said second control line and said first control line have been processed following the same lithography step and accordingly are self-aligned,

wherein said first control line is directly connected to each source or drain of at least five of said first transistors, and

wherein said second control line is directly connected to each source or drain of at least five of said second transistors; and

an oxide layer disposed between said first control line and said second control line,

wherein said second transistors comprise a poly-silicon transistor channel.

16. The 3D semiconductor memory according to claim 15 ,

wherein said second transistors each comprise a double gate.

17. The 3D semiconductor memory according to claim 15 ,

wherein at least one of said first transistors is self-aligned to at least one of said second transistors, having been processed following the same lithography step.

18. The 3D semiconductor memory according to claim 15 , further comprising:

a plurality of metalized memory control lines; and

a single crystal silicon substrate,

wherein said plurality of metalized memory control lines are primarily disposed between said single crystal silicon substrate and said first level.

19. The 3D semiconductor memory according to claim 15 ,

wherein said first control line comprises silicon.

20. The 3D semiconductor memory according to claim 15 , further comprising:

a single crystal silicon substrate,

wherein said single crystal silicon substrate comprises third transistors, and

wherein at least one of said third transistors is disposed directly below at least a portion of said first transistors.

Assignments (1)

Continuity (8)

References Cited (400)