Transistors with stacked semiconductor layers as channels

1. A method of forming a semiconductor device, the method comprising:

depositing a first p-type semiconductor layer over a portion of a semiconductor substrate;

depositing a first semiconductor layer over the first p-type semiconductor layer, wherein the first semiconductor layer is free from p-type impurities;

forming a gate stack directly over a first portion of the first semiconductor layer;

etching a second portion of the first semiconductor layer to form a trench extending into the first semiconductor layer, wherein at least a surface of the first p-type semiconductor layer is exposed to the trench; and

forming a source/drain region in the trench, wherein the source/drain region is of n-type.

2. The method of claim 1 further comprising depositing a second semiconductor layer over the portion of the semiconductor substrate, wherein the second semiconductor layer is further free from p-type impurities, and the second semiconductor layer is underlying and in contact with the first p-type semiconductor layer.

3. The method of claim 2 , wherein in the etching, the first p-type semiconductor layer is further etched-through, and a top surface of the second semiconductor layer is exposed to the trench.

4. The method of claim 2 , wherein a bottom surface of the trench is higher than a bottom surface of the second semiconductor layer.

5. The method of claim 1 , wherein the etching stops on a top surface of the first p-type semiconductor layer.

6. The method of claim 1 further comprising depositing a second p-type semiconductor layer over the first semiconductor layer.

7. The method of claim 6 , further comprising depositing a second semiconductor layer over the second p-type semiconductor layer, wherein the second semiconductor layer is free from p-type impurities.

8. The method of claim 7 further comprising forming a gate electric over and contacting the second semiconductor layer.

9. The method of claim 7 further comprising etching a dummy gate stack over the second semiconductor layer, wherein the second semiconductor layer is etched-through, and the etching stops on a top surface of the second p-type semiconductor layer.

10. The method of claim 1 , wherein the first p-type semiconductor layer is further free from n-type impurities.

11. A method of forming a semiconductor device, the method comprising:

forming isolation regions extending into a semiconductor substrate;

etching to remove a portion of the semiconductor substrate between the isolation regions to form a trench;

performing a first epitaxy to grow a first semiconductor layer in the trench, wherein the first semiconductor layer is free from p-type impurities and n-type impurities;

performing a second epitaxy to grow a first SiB layer over and contacting the first semiconductor layer;

performing a third epitaxy to grow a second semiconductor layer over the first SiB layer, wherein the second semiconductor layer is free from p-type impurities and n-type impurities; and

recessing the isolation regions, so that the second semiconductor layer and a portion of the first SiB layer are higher than top surfaces of the isolation regions to form a semiconductor fin.

12. The method of claim 11 , wherein in the recessing the isolation regions, a first portion of the first semiconductor layer is higher than the top surfaces of the isolation regions to form a portion of the semiconductor fin.

13. The method of claim 12 , wherein in the recessing the isolation regions, a second portion of the first semiconductor layer is lower than the top surfaces of the isolation regions.

14. The method of claim 11 further comprising:

forming a gate stack overlapping a first portion of the first semiconductor layer;

performing an etching process using the gate stack as a part of an etching mask to form an additional trench, wherein in the etching process, the second semiconductor layer is etched-through, and a surface of the first SiB layer is exposed to the additional trench; and

forming a source/drain region in the additional trench, wherein the source/drain region is of n-type.

15. The method of claim 14 further comprising:

performing a fourth epitaxy to grow a second SiB layer over the second semiconductor layer; and

performing a fifth epitaxy to grow a third semiconductor layer over the second SiB layer, wherein the third semiconductor layer is free from p-type impurities and n-type impurities.

16. A method comprising:

forming isolation regions extending into a semiconductor substrate;

forming a semiconductor strip between the isolation regions, wherein the semiconductor strip comprises a semiconductor fin protruding higher than top surfaces of the isolation regions, and wherein the forming the semiconductor strip comprises:

epitaxially growing a first semiconductor layer, the first semiconductor layer being free from p-type impurities; and

epitaxially growing a first p-type semiconductor layer over and contacting the first semiconductor layer;

forming a gate stack on a top surface and sidewalls of the semiconductor fin; and

epitaxially growing a source/drain region extending into the semiconductor fin, wherein the source/drain region contacts the first p-type semiconductor layer, and the source/drain region is an n-type region.

17. The method of claim 16 further comprising etching the semiconductor strip to form a recess, wherein the source/drain region is epitaxially grown from the recess.

18. The method of claim 16 , wherein when the source/drain region is grown, a portion of the first semiconductor layer is directly underlying the recess.

19. The method of claim 18 , wherein when the source/drain region is grown, an additional portion of the first p-type semiconductor layer is directly underlying the recess.

20. The method of claim 16 , wherein the forming the semiconductor strip further comprises:

epitaxially growing a second semiconductor layer over the first p-type semiconductor layer, the second semiconductor layer being free from p-type impurities; and

epitaxially growing a second p-type semiconductor layer over and contacting the second semiconductor layer.