Memory devices with multiple sets of latencies and methods for operating the same
Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
1. A method of operating a memory device, comprising:
enabling one or more memory operation features from a set of memory operation features;
determining a numeric count of the one or more memory operation features that are enabled;
applying a first set of a plurality of sets of latency values when the numeric count of the one or more memory operation features that are enabled is equal to a first number;
applying a second set of the plurality of sets of latency values different from the first set when the numeric count of the one or more memory operation features that are enabled is equal to a second number different from the first number; and
executing a read command or a write command for one or more cells of the memory device based at least in part on the enabled memory operation features and the applied first or second set of latency values.
2. The method of claim 1 , further comprising:
identifying a lower limit for a clock signal and an upper limit for the clock signal;
determining a setting for a mode register from a plurality of mode registers of the memory device, wherein the setting for the mode register comprises a four-bit value; and
operating the memory device at a frequency that is not less than the lower limit for the clock signal nor greater than the upper limit for the clock signal irrespective of the setting for the mode register.
3. The method of claim 1 , further comprising:
determining whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled, wherein the plurality of sets of latency values is based at least in part on whether DVFS is disabled or enabled.
4. The method of claim 1 , wherein the one or more memory operation features comprises at least one of a byte mode feature, a read data bus inversion feature, a read data copy feature, a read link error correction feature, or any combination thereof.
5. The method of claim 1 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a mode register setting from a plurality of mode register settings of the memory device.
6. The method of claim 1 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the memory device.
7. The method of claim 1 , wherein the one or more memory operation features comprises at least two features, and wherein the plurality of sets of latency values comprises a corresponding at least two sets of latency values.
8. The method of claim 7 , wherein the at least two sets of latency values comprise at least three sets of latency values, and wherein the method comprises applying a first one of the at least three sets of latency values when none of the at least two features is enabled, applying a second one of the at least three sets of latency values when exactly one of the at least two features is enabled, and applying a third one of the at least three sets of latency values when exactly two of the at least two features is enabled.
9. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of read latency values.
10. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of write latency values.
11. The method of claim 1 , wherein the plurality of sets of latency values comprises a plurality of sets of write recovery times.
12. A memory device, comprising:
a memory array; and
control circuitry configured to:
enable one or more memory operation features from a set of memory operation features;
determine a numeric count of the one or more memory operation features that are enabled;
apply a first set of a plurality of sets of latency values when the numeric count of the one or more memory operation features that are enabled is equal to a first number; and
apply a second set of the plurality of sets of latency values different from the first set when the numeric count of the one or more memory operation features that are enabled is equal to a second number different from the first number.
13. The memory device of claim 12 , wherein the control circuitry is further configured to:
execute a read command or a write command for one or more cells of the memory array based at least in part on the enabled memory operation features and the applied first or second set of latency values.
14. The memory device of claim 12 , wherein the control circuitry is further configured to:
identify a lower limit for a clock signal and an upper limit for the clock signal;
determine a setting for a mode register from a plurality of mode registers of the memory device, wherein the setting for the mode register comprises a four-bit value; and
operate the memory device at a frequency that is not less than the lower limit for the clock signal nor greater than the upper limit for the clock signal irrespective of the setting for the mode register.
15. The memory device of claim 12 , wherein the control circuitry is further configured to:
determine whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled, wherein the plurality of sets of latency values is based at least in part on whether DVFS is disabled or enabled.
16. The memory device of claim 12 , wherein the memory array and the control circuitry are located on a single semiconductor die.
17. The memory device of claim 12 , wherein the memory array and the control circuitry are located on separate semiconductor dies.
18. The memory device of claim 17 , wherein the separate semiconductor dies are located on a single memory module.
19. The memory device of claim 12 , wherein the one or more memory operation features comprises at least one of a byte mode feature, a read data bus inversion feature, a read data copy feature, a read link error correction feature, or any combination thereof.
20. The memory device of claim 12 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a mode register setting from a plurality of mode register settings of the memory device.
21. The memory device of claim 12 , wherein each set of latency values of the plurality of sets of latency values includes a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the memory device.
22. The memory device of claim 12 , wherein the one or more selectable features comprises at least two selectable features, and wherein the plurality of sets of latency values comprises at least two sets of latency values.
23. The memory device of claim 21 , wherein the at least two sets of latency values comprise at least three sets of latency values, and wherein the control circuitry is configured to apply a first one of the at least three sets of latency values when none of the at least two memory operation features is enabled, to apply a second one of the at least three sets of latency values when exactly one of the at least two memory operation features is enabled, and to apply a third one of the at least three sets of latency values when exactly two of the at least two sets of latency values are enabled.
24. The memory device of claim 12 , wherein the plurality of sets of latency values comprises a plurality of sets of read latency values.
25. The memory device of claim 12 , wherein the plurality of sets of latency values comprises a plurality of sets of write latency values.
26. The memory device of claim 12 , wherein the plurality of sets of latency values comprises a plurality of sets of write recovery times.
27. A memory system, comprising:
at least one of a general purpose processor, an application processor, a baseband processor, or a combination thereof; and
a memory device coupled thereto by a memory bus, wherein the memory device includes a memory array and control circuitry coupled to the memory array, the control circuitry configured to:
enable one or more memory operation features from a set of memory operation features;
determine a numeric count of the one or more memory operation features that are enabled;
apply a first set of a plurality of sets of latency values when the numeric count of the one or more memory operation features that are enabled is equal to a first number; and
apply a second set of the plurality of sets of latency values different from the first set when the numeric count of the one or more memory operation features that are enabled is equal to a second number different from the first number.
28. The memory system of claim 27 , wherein the control circuitry is further configured to:
execute a read command or a write command for one or more cells of the memory array based at least in part on the enabled memory operation features and the applied first or second set of latency values.
29. The memory system of claim 27 , wherein the control circuitry is further configured to enable the one or more memory operation features based at least in part on which of the general purpose processor, the application processor, or the baseband processor sends the read command or the write command to the memory device.
30. The memory system of claim 27 , wherein the control circuitry is further configured to enable the one or more memory operation features based at least in part on detecting a connection to one of the general purpose processor, the application processor, or the baseband processor.
31. The memory system of claim 27 , wherein the memory system is a wireless communication device further comprising a modem coupled to the baseband processor.