IP Library Granted Patent US 10,658,459
Granted Patent B2
US 10,658,459 · App. 16/545,867 · Granted May 19, 2020

Nanosheet transistor with robust source/drain isolation from substrate

Inventors: Robin Hsin Kuo Chao (Cohoes, NY); Kangguo Cheng (Schenectady, NY); Cheng Chi (Jersey City, NJ); Ruilong Xie (Yorktown Heights, NY); John H. Zhang (Albany, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/0653H01L29/0669H01L29/66439H01L29/775
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Quick Facts
Patent No.
US 10,658,459
App. No.
16/545,867
Granted
May 19, 2020
Kind
B2
Abstract

A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

Claims (28)

1. An apparatus, comprising:

a substrate structure having a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers, the substrate structure including at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;

a u-shaped portion formed at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;

a first liner disposed upon the u-shaped portion of the at least one trench;

a second liner disposed on the first liner; and

a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

2. The apparatus of claim 1 , further comprising:

a plurality of recesses disposed between the nanosheet layers, wherein the third liner is further disposed within the plurality of recesses to form a plurality of inner spacers between the nanosheet layers.

3. The apparatus of claim 1 , further comprising:

a source/drain epitaxy disposed upon the bottom inner spacer.

4. The apparatus of claim 1 , further comprising:

a gate material disposed between the nanosheet layers.

5. The apparatus of claim 1 , further comprising:

an insulative cap disposed upon a top nanosheet of the plurality of nanosheets;

an interlayer dielectric layer disposed upon the insulative cap; and

at least one contact formed within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.

6. An apparatus, comprising:

a substrate structure having a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers, the substrate structure including at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;

a u-shaped portion formed at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;

a first liner disposed upon the u-shaped portion of the at least one trench;

a second liner disposed on the first liner;

a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity;

a plurality of recesses disposed between the nanosheet layers, wherein the third liner is further disposed within the plurality of recesses to form a plurality of inner spacers between the nanosheet layers;

a source/drain epitaxy disposed upon the bottom inner spacer;

a gate material disposed between the nanosheet layers;

an insulative cap disposed upon a top nanosheet of the plurality of nanosheets;

an interlayer dielectric layer disposed upon the insulative cap; and

at least one contact formed within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.

Assignments (2)
RECORDABLE PATENT ASSIGNMENT AND RESERVATION Recorded Jan 9, 2023
From: INTERNATIONAL BUSINESS MACHINES CORPORATION,
To: RAPIDUS CORPORATION
Reel/Frame 062323/0067 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2019
From: CHAO, ROBIN HSIN KUO; CHENG, KANGGUO; CHI, CHENG; XIE, RUILONG; ZHANG, JOHN H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 050107/0112 →
Continuity (2)
Division 15967524 · Apr 30, 2018
Related Publication 20200006476A1 · Jan 2, 2020
Cited By (1)
US 12,191,368