Always-on audio control for mobile device
In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
1. An integrated circuit comprising:
one or more processors;
at least one memory controller; and
a first circuit coupled to the one or more processors and to the memory controller, wherein:
the first circuit is configured to remain powered up during times that the one or more processors and the memory controller are powered down;
the first circuit is configured to receive audio samples captured by one or more audio input devices and to detect a predetermined pattern in the audio samples during a time that the one or more processors and the memory controller are powered down;
the first circuit is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern; and
the first circuit is configured to: buffer the audio samples that match the predetermined pattern and subsequently-received samples while the memory controller initializes, write the audio samples that match the predetermined pattern and the subsequently-received samples to memory through the memory controller, and continue writing audio samples received after the memory controller initializes, providing a loss-free series of samples beginning with at least the audio samples that match the predetermined pattern for processing by the one or more processors.
2. The integrated circuit as recited in claim 1 wherein the loss-free series of samples includes one or more audio samples that precede the audio samples that match the predetermined pattern.
3. The integrated circuit as recited in claim 1 wherein the first circuit is configured to buffer a number of audio samples sufficient to store the audio samples that match the predetermined pattern and the subsequently-received samples until the memory controller is available to receive writes of the audio samples to the memory.
4. The integrated circuit as recited in claim 1 wherein the one or more processors are configured to access the loss-free series of samples in the memory to verify the match subsequent to powering up responsive to the first circuit detecting the match.
5. The integrated circuit as recited in claim 1 wherein the predetermined pattern represents sound comprising a verbal utterance of one or more words.
6. The integrated circuit as recited in claim 5 wherein the predetermined pattern is captured from a voice of a user.
7. The integrated circuit as recited in claim 1 wherein the predetermined pattern represents a non-verbal sound.
8. The integrated circuit as recited in claim 1 wherein the first circuit is configured to provide one or more memory controller parameters to the memory controller to program the memory controller for operation with the memory.
9. The integrated circuit as recited in claim 1 wherein the first circuit comprises a processor configured to execute a plurality of instructions to perform at least the detecting of the predetermined pattern in the audio samples and causing the power up of the processors and the memory controller.
10. The integrated circuit as recited in claim 1 wherein the first circuit comprises hardware circuitry configured to detect the predetermined pattern in the audio samples.
11. A system comprising:
an audio input device;
an audio coder/decoder (codec) coupled to the audio input device and configured to generate audio samples from sound detected by the audio input device;
a memory; and
an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes an audio filter, one or more processors, and a memory controller coupled to the memory;
the audio filter is configured to detect a predetermined pattern in the audio samples from the audio codec during a time that the memory controller and the one or more processors are powered down and is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern; and
the audio filter is configured to: buffer the audio samples that match the predetermined pattern and subsequently-received samples while the memory controller initializes, write the audio samples that match the predetermined pattern and the subsequently-received samples to memory through the memory controller, and continue writing audio samples received after the memory controller initializes, providing a loss-free series of samples beginning with at least the audio samples that match the predetermined pattern for processing by the one or more processors.
12. The system as recited in claim 11 wherein the one or more processors are configured to access the audio samples in the memory to verify the match subsequent to powering up responsive to the audio filter detecting the match.
13. The system as recited in claim 11 wherein the audio filter is configured to supply a plurality of memory controller parameters to the memory controller to program the memory controller for operation, wherein the audio filter is configured to generate write operations subsequent to programming the memory controller.
14. The system as recited in claim 11 wherein the audio input device is one of a plurality of microphones included in the system, and wherein other ones of the plurality of microphones are disabled during times that the memory controller is powered down.
15. The system as recited in claim 11 wherein the predetermined pattern represents sound comprising a verbal utterance of one or more words.
16. The system as recited in claim 15 wherein the predetermined pattern is captured from a voice of a user.
17. A method comprising:
receiving audio samples captured by one or more audio input devices in a first circuit in an integrated circuit;
detecting a predetermined pattern in the audio samples by the first circuit during a time that one or more processors in the integrated circuit and a memory controller in the integrated circuit are powered down;
causing the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern;
buffering the audio samples that match the predetermined pattern and subsequently-received samples in the first circuit while the memory controller initializes;
writing the audio samples that match the predetermined pattern and the subsequently-received samples from the first circuit to memory through the memory controller; and
continuing to write audio samples received after the memory controller initializes from the first circuit to the memory through the memory controller, providing a loss-free series of samples beginning with at least the audio samples that match the predetermined pattern for processing by the one or more processors.
18. The method as recited in claim 17 further comprising:
booting an operating system on the one or more processors; and
processing the buffered audio samples from the memory by the one or more processors subsequent to the booting.
19. The method as recited in claim 18 wherein the processing comprises:
verifying that the predetermined pattern is detected by the one or more processors; and
interpreting the subsequently-received samples by the one or more processors.
20. The method as recited in claim 17 wherein the loss-free series of samples includes one or more audio samples that precede the audio samples that match the predetermined pattern.