Semiconductor device and manufacturing method thereof

1. A semiconductor device, comprising:

a substrate;

a source/drain structure over the substrate;

a source/drain contact over the source/drain structure;

a gate structure over the substrate;

a protective cap over the gate structure;

a first etching stop layer over the protective cap, wherein the first etching stop layer comprises a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion; and

a via contact over the source/drain contact, wherein the via contact has a stepped sidewall structure comprising an upper sidewall, a lower sidewall laterally set back from the upper sidewall, and an intermediary surface laterally extending from a bottom end of the upper sidewall to a top end of the lower sidewall, wherein the lower sidewall of the via contact is in contact with the first portion of the first etching stop layer, and wherein the via contact comprises a bottom corner, and the bottom corner has a rounded profile extending from a top surface of the second portion of the first etching stop layer to a top surface of the first portion of the first etching stop layer.

2. The semiconductor device of claim 1 , further comprising a second etching stop layer over and in contact with the first etching stop layer.

3. The semiconductor device of claim 2 , wherein the second etching stop layer is in contact with the second portion of the first etching stop layer and is separated from the first portion of the first etching stop layer.

4. The semiconductor device of claim 1 , wherein the via contact comprises a protrusion portion in contact with the source/drain contact, and a bottom surface of the protrusion portion is lower than a bottom surface of the first etching stop layer.

5. The semiconductor device of claim 4 , wherein the protective cap is between the first etching stop layer and the gate structure, wherein the protrusion portion of the via contact is in contact with the protective cap.

6. A semiconductor device, comprising:

a substrate;

a source/drain structure over the substrate;

a source/drain contact over the source/drain structure;

a gate structure over the substrate;

gate spacers on opposite sidewalls of the gate structure;

a protective cap over the gate structure, wherein the protective cap comprises a lower portion laterally between the gate spacers and an upper portion above the gate spacers;

a first etching stop layer over the protective cap; and

a via contact over the first etching stop layer, wherein a horizontal interface between the via contact and the first etching stop layer is lower than a top-most surface of the first etching stop layer.

7. The semiconductor device of claim 6 , wherein the via contact comprises a protrusion portion extending to a position lower than the horizontal interface between the via contact and the first etching stop layer.

8. The semiconductor device of claim 6 , further comprising a second etching stop layer over and in contact with the top-most surface of the first etching stop layer.

9. The semiconductor device of claim 6 , wherein the horizontal interface between the via contact and the first etching stop layer is higher than a bottom-most surface of the first etching stop layer.

10. The semiconductor device of claim 1 , further comprising:

a gate spacer on a sidewall of the gate structure, wherein the protective cap is vertically between the gate spacer and the first etching stop layer, wherein the via contact extends along a sidewall of the protective cap.

11. The semiconductor device of claim 1 , wherein the via contact extends along a sidewall of the first portion of the first etching stop layer.

12. The semiconductor device of claim 1 , wherein the top surface of the second portion of the first etching stop layer is free of coverage of the via contact.

13. A semiconductor device, comprising:

a substrate;

a source/drain structure over the substrate;

a gate structure over the substrate;

gate spacers on opposite sidewalls of the gate structure;

a first etching stop layer over the gate structure, wherein the first etching stop layer comprises a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion;

a second etching stop layer over the first etching stop layer, wherein the second etching stop layer is in contact with a top surface of the second portion of the first etching stop layer and is separated from a top surface of the first portion of the first etching stop layer; and

a contact via over the gate structure, wherein the contact via is in contact with the top surface of the first portion of the first etching stop layer and a sidewall of the second portion of the first etching stop layer, and is separated from the gate spacers.

14. The semiconductor device of claim 13 , further comprising an interlayer dielectric layer over the second etching stop layer, wherein the interlayer dielectric layer does not vertically overlap the first portion of the first etching stop layer.

15. The semiconductor device of claim 13 , further comprising:

a protective cap over the gate structure and the gate spacers and below the first etching stop layer, wherein the contact via is in contact with a sidewall of the protective cap.

16. The semiconductor device of claim 13 , wherein the first etching stop layer and the second etching stop layer are made of different materials.

17. The semiconductor device of claim 1 , wherein the protective cap is in contact with the via contact.

18. The semiconductor device of claim 1 , further comprising a gate spacer on a sidewall of the gate structure, wherein the protective cap is vertically between the first etching stop layer and the gate spacer.

19. The semiconductor device of claim 18 , wherein the protective cap is in contact with the via contact and a top surface of the gate spacer.

20. The semiconductor device of claim 1 , wherein the source/drain contact comprises a liner and a plug over the liner.