Methods and devices for in-phase and quadrature signal generation
A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.
1. An in-phase and quadrature signal generation system comprising:
a first stage configured to:
receive a first set of differential input signals; and
generate a first set of differential in-phase/quadrature (I/Q) output signals; and
a second stage configured to:
receive the first set of differential I/Q output signals; and
generate a second set of differential I/Q output signals;
wherein the amplitude and phase mismatches between the second set of differential I/Q output signals is less than the amplitude and phase mismatches between the first set of differential I/Q output signals, compensating for quadrature errors of the first set of differential I/Q output signals;
wherein the first stage comprises:
a first coupled line coupler (CLC); and
a second CLC;
wherein each CLC comprises:
a pair of transmission lines close enough in proximity so when energized, energy from one of the transmission lines passes to the other transmission line;
an inlet port directly coupled to a through port across one of the pair of transmission lines;
a coupled port coupled to the inlet port; and
an isolation port directly connected to the coupled port across transmission line;
wherein the isolation port is terminated to an optimum impedance; and
wherein the signal generation system is configured to:
generate the second set of differential I/Q output signals at mm-wave frequencies; and
achieve an image rejection ratio of more than 29 across a frequency range of between 42-102 GHz.
2. The system of claim 1 , wherein the first stage is further configured to maintain the frequency of the second set of differential output signals the same as the frequency of the first set of differential I/Q input signals;
wherein the first set of differential input signals comprises a first input signal and a second input signal; and
wherein the first input signal has a phase shift relative to the second input signal.
3. The system of claim 2 , wherein the first input signal of the first set of differential input signals has a phase shift of or about 180 degrees relative to the second input signal; and
wherein the second set of differential I/Q output signals comprise:
a first output signal having a phase shift of or about ninety degrees relative to a second output signal;
the second output signal having a phase shift of or about ninety degrees relative to a third output signal;
the third output signal having a phase shift of or about ninety degrees relative to a fourth output signal; and
the fourth output signal having a phase shift of or about ninety degrees relative to the first output signal.
4. The system of claim 1 , wherein the second stage comprises a resistor-capacitor (RC) polyphase filter.
5. The system of claim 4 , wherein a physical implementation of the RC polyphase filter has a symmetrical layout with respect to a center of the polyphase filter.
6. An in-phase and quadrature signal generation system comprising:
a first stage configured to:
receive a first set of differential input signals, wherein the first set of differential input signals comprises a first input signal having a phase shift of or about 180 degrees relative to a second input signal; and
generate a first set of differential in-phase/quadrature (I/Q) output signals; and
a second stage configured to:
receive the first set of differential I/Q output signals; and
generate a second set of differential I/Q output signals comprising:
a first output signal having a phase shift of or about ninety degrees relative to a second output signal;
the second output signal having a phase shift of or about ninety degrees relative to a third output signal;
the third output signal having a phase shift of or about ninety degrees relative to a fourth output signal; and
the fourth output signal having a phase shift of or about ninety degrees relative to the first output signal
wherein the first stage is further configured to maintain the frequency of the second set of differential I/Q output signals the same as the frequency of the first set of differential I/Q input signals;
wherein the amplitude and phase mismatches between the second set of differential I/Q output signals is less than the amplitude and phase mismatches between the first set of differential I/Q output signals, compensating for quadrature errors of the first set of differential I/Q output signals;
wherein the second stage comprises:
a first coupled line coupler (CLC);
a second CLC;
a third CLC; and
a fourth CLC;
wherein each CLC comprises:
a pair of transmission lines close enough in proximity so when energized, energy from one of the transmission lines passes to the other transmission line;
an inlet port directly coupled to a through port across one of the pair of transmission lines;
a coupled port coupled to the inlet port; and
an isolation port directly connected to the coupled port across transmission line;
wherein the isolation port is terminated to an optimum impedance; and
wherein the signal generation system is configured to:
generate the second set of differential I/Q output signals at mm-wave frequencies; and
achieve an image rejection ratio of more than 29 across a frequency range of between 42-102 GHz.
7. The system of claim 6 , wherein:
the coupled port of the second CLC is connected to the through port of the first CLC;
the coupled port of the third CLC is connected to the through port of the second CLC;
the coupled port of the fourth CLC is connected to the through port of the third CLC; and
the coupled port of the first CLC is connected to the through port of the fourth CLC.
8. A receiver comprising:
an antenna configured to receive signals;
an amplifier configured to receive signals from the antenna;
an in-phase down-conversion path comprising:
a first mixer;
a first filter; and
a first baseband unit;
a quadrature down-conversion path comprising:
a second mixer;
a second filter; and
a second baseband unit; and
an in-phase and quadrature (I/Q) signal generation path comprising:
a synthesizer; and
the signal generation system of claim 6 ;
wherein the signal generation system is configured to generate:
differential in-phase (I) local oscillator (LO) signals (ILO signals); and
differential quadrature (Q) local oscillator (LO) signals (QLO signals).
9. A transmitter comprising:
an antenna configured to transmit signals;
an amplifier configured to send signals to the antenna;
an in-phase up-conversion path comprising:
a first mixer;
a first filter; and
a first baseband unit;
a quadrature up-conversion path comprising:
a second mixer;
a second filter; and
a second baseband unit; and
an in-phase and quadrature (I/Q) signal generation path comprising:
a synthesizer; and
the signal generation system of claim 6 ;
wherein the signal generation system is configured to generate:
differential in-phase (I) local oscillator (LO) signals (ILO signals); and
differential quadrature (Q) local oscillator (LO) signals (QLO signals).
10. An in-phase and quadrature signal generation system comprising:
a first stage configured to:
receive a first set of differential input signals; and
generate a first set of differential in-phase/quadrature (I/Q) output signals; and
a second stage configured to:
receive the first set of differential I/Q output signals; and
generate a second set of differential I/Q output signals;
wherein the amplitude and phase mismatches between the second set of differential I/Q output signals is less than the amplitude and phase mismatches between the first set of differential I/Q output signals, compensating for quadrature errors of the first set of differential I/Q output signals; and
wherein the first stage comprises:
a first coupled line coupler (CLC); and
a second CLC;
wherein each CLC comprises:
a pair of transmission lines close enough in proximity so when energized, energy from one of the transmission lines passes to the other transmission line;
an inlet port directly coupled to a through port across one of the pair of transmission lines;
a coupled port coupled to the inlet port; and
an isolation port directly connected to the coupled port across transmission line;
wherein the isolation port is terminated to an optimum impedance.
11. The system of claim 10 , wherein the second stage comprises a resistor-capacitor (RC) polyphase filter.
12. The system of claim 11 , wherein the signal generation system is configured to:
generate the second set of differential I/Q output signals at mm-wave frequencies; and
achieve an image rejection ratio of more than 29 across a frequency range of between 36-98 GHz.
13. The system of claim 10 , wherein each CLC is selected from the group consisting of an edge-coupler, a broadside-coupler, and a Lange-coupler.
14. The system of claim 10 , wherein a physical implementation of the first and second CLC has a symmetrical layout with respect to a center of the first stage.
15. The system of claim 10 , wherein the second stage comprises:
a first CLC;
a second CLC;
a third CLC; and
a fourth CLC;
wherein the coupled port of the second CLC is connected to the through port of the first CLC;
wherein the coupled port of the third CLC is connected to the through port of the second CLC;
wherein the coupled port of the fourth CLC is connected to the through port of the third CLC; and
wherein the coupled port of the first CLC is connected to the through port of the fourth CLC.
16. The system of claim 15 , wherein the signal generation system is configured to generate the second set of differential I/Q output signals at mm-wave frequencies;
wherein the first stage is further configured to maintain the frequency of the first set of differential input signals the same as the frequency of the first set of differential I/Q output signals;
wherein the first set of differential input signals comprises a first input signal and a second input signal;
wherein the first input signal has a phase shift of or about 180 degrees relative to the second input signal;
wherein the second set of differential I/Q output signals comprise:
a first output signal having a phase shift of or about ninety degrees relative to a second output signal;
the second output signal having a phase shift of or about ninety degrees relative to a third output signal;
the third output signal having a phase shift of or about ninety degrees relative to a fourth output signal; and
the fourth output signal having a phase shift of or about ninety degrees relative to the first output signal.
17. The system of claim 15 , wherein each CLC of the first and second stages is selected from the group consisting of an edge-coupler, a broadside-coupler, and a Lange-coupler.
18. The system of claim 15 , wherein a physical implementation of the first and second CLC of the first stage has a symmetrical layout with respect to a center of the first stage; and
wherein a physical implementation of the first, second, third and fourth CLC of the second stage has a symmetrical layout with respect to the center of the first stage.
19. The system of claim 10 , wherein the signal generation system is configured to generate the second set of differential I/Q output signals at mm-wave frequencies;
wherein the first stage is further configured to maintain the frequency of the first set of differential input signals the same as the frequency of the first set of differential I/Q output signals;
wherein the first set of differential input signals comprises a first input signal and a second input signal;
wherein the first input signal has a phase shift of or about 180 degrees relative to the second input signal;
wherein the second set of differential I/Q output signals comprise:
a first output signal having a phase shift of or about ninety degrees relative to a second output signal;
the second output signal having a phase shift of or about ninety degrees relative to a third output signal;
the third output signal having a phase shift of or about ninety degrees relative to a fourth output signal; and
the fourth output signal having a phase shift of or about ninety degrees relative to the first output signal.
20. A receiver comprising:
an antenna configured to receive signals;
an amplifier configured to receive signals from the antenna;
an in-phase down-conversion path comprising:
a first mixer;
a first filter; and
a first baseband unit;
a quadrature down-conversion path comprising:
a second mixer;
a second filter; and
a second baseband unit; and
an in-phase and quadrature (I/Q) signal generation path comprising:
a synthesizer; and
the signal generation system of claim 10 ;
wherein the signal generation system is configured to generate:
differential in-phase (I) local oscillator (LO) signals (ILO signals); and
differential quadrature (Q) local oscillator (LO) signals (QLO signals).
21. A transmitter comprising:
an antenna configured to transmit signals;
an amplifier configured to send signals to the antenna;
an in-phase up-conversion path comprising:
a first mixer;
a first filter; and
a first baseband unit;
a quadrature up-conversion path comprising:
a second mixer;
a second filter; and
a second baseband unit; and
an in-phase and quadrature (I/Q) signal generation path comprising:
a synthesizer; and
the signal generation system of claim 10 ;
wherein the signal generation system is configured to generate:
differential in-phase (I) local oscillator (LO) signals (ILO signals); and
differential quadrature (Q) local oscillator (LO) signals (QLO signals).
22. A transceiver comprising:
the signal generation system of claim 10 ; and
a first and second mixer;
wherein each mixer comprises a switching core circuit comprising a set of transistors and interconnects;
wherein each transistor of the set of transistors comprises a base, an emitter and a collector;
wherein each interconnect is selected from the group consisting of a base interconnect, a collector interconnect, and an emitter interconnect;
wherein the switching core circuit is configured to receive a set of amplified signals and a set of differential in-phase and quadrature (I/Q) local oscillator (LO) signals;
wherein the set of differential in-phase and quadrature (I/Q) local oscillator (LO) signals comprise:
a positive in-phase (I+) signal;
a positive quadrature (Q+) signal;
a negative in-phase (I−) signal; and
a negative quadrature (Q−);
wherein the base interconnects of a first transistor and a second transistor of the set of transistors are configured to receive the I+ signal;
wherein the base interconnects of a third transistor and a fourth transistor of the set of transistors are configured to receive the Q+ signal;
wherein the base interconnects of a fifth transistor and a sixth transistor of the set of transistors are configured to receive the I− signal; and
wherein the base interconnects of a seventh transistor and an eighth transistor of the set of transistors are configured to receive the Q− signal;
wherein the emitter interconnect of the second transistor is connected to the emitter interconnect of the third transistor;
wherein the emitter interconnect of the fourth transistor is connected to the emitter interconnect of the fifth transistor;
wherein the emitter interconnect of the sixth transistor is connected to the emitter interconnect of the seventh transistor;
wherein the emitter interconnect of the eighth transistor is connected to the emitter interconnect of the first transistor;
wherein the collector interconnect of the first transistor is connected to the collector interconnect of the sixth transistor;
wherein the collector interconnect of the second transistor is connected to the collector interconnect of the fifth transistor;
wherein the collector interconnect of the third transistor is connected to the collector interconnect of the eighth transistor; and
wherein the collector interconnect of the fourth transistor is connected to the collector interconnect of the seventh transistor.
23. The transceiver of claim 22 , wherein a physical implementation of switching core circuit has a symmetric layout with respect to its center.
24. The transceiver of claim 23 , wherein the base interconnects have the same length;
wherein the collector interconnects have the same length; and
wherein the emitter interconnects have the same length.