Self-aligned vertical solid state devices fabrication and integration methods
Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.
1. A method of fabricating a self-aligned vertical solid state device, the method comprising:
providing a substrate;
depositing a plurality of device layers on the substrate;
depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the plurality of device layers comprises an active layer and a doped conductive layer;
depositing a metal conductive layer on top of the ohmic contact layer or the doped conductive layer;
patterning the metal conductive layer;
patterning the doped conductive layer, the doped conductive layer comprising a hard masking layer and a photoresist layer by depositing the hard masking layer over the metal conductive layer, depositing a patterned photoresist layer on the hard masking layer, to cover an epitaxial layer and the substrate, and patterning the metal conductive layer using the hard masking layer to define a contact area of the device;
depositing conformally a passivation layer covering the upper surface of the plurality of device layers and other layers formed on the surface;
removing back the passivation layer to expose a top of the metal conductive layer;
etching the passivation layer or the dielectric layer formed on the top of the metal conductive layer;
removing the hard masking layer;
depositing a first dielectric layer on the photoresist layer;
depositing another conductive layer after the first dielectric layer;
depositing a second dielectric layer after the deposition of the other conductive layer; and
biasing the other conductive layer to isolate an area associated with the ohmic contact layer.
2. The method of claim 1 , wherein the ohmic contact layer comprises an indium tin oxide layer as another ohmic contact.
3. The method of claim 1 , further comprising:
depositing a plurality of other layers conformally over the plurality of device layers after removing the hard masking layer;
wherein the deposited other layers are patterned over the plurality of device layers to remove extra layers from a top of a plurality of patterned conductive layers.
4. The method of claim 3 , wherein the plurality of other layers comprising:
one or more passivation layers, polymer layers, dielectric layers, conductive layers and reflective layers.
5. The method of claim 1 , further comprising
etching a bottom layer of one of the plurality of device layers to expose bottom contacts, wherein the bottom layer comprises: one of a bottom conductive layer or a bottom doped layer.
6. The method of claim 5 , wherein the bottom layer is a n-type ohmic layer.
7. The method of claim 1 , wherein the vertical solid state device is a microLED device.
8. The method of claim 1 , wherein the etching is a wet etching, a dry etching or a laser ablation.
9. The method of claim 1 , wherein the fabricated self-aligned vertical solid state device comprises straight walls or sloped walls.