Semiconductor device with bonding pads and method of manufacturing the same
A semiconductor device includes: a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate; a memory cell provided above the logic circuit and a second semiconductor substrate provided above the memory cell; a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit; and a wiring provided above the second semiconductor substrate. The wiring is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.
1. A semiconductor device, comprising:
a first chip including a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate;
a second chip bonded on the first chip and including a memory cell array and a second semiconductor substrate provided above the memory cell array;
a plurality of bonding metals provided on a bonding surface of the first chip and the second chip;
a plurality of plugs extending through the second semiconductor substrate;
a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit via a first bonding metal of the plurality of bonding metals and a first plug of the plurality of plugs; and
a wiring provided above the second semiconductor substrate, electrically connected to the logic circuit via a second bonding metal of the plurality of bonding metals and a second plug of the plurality of plugs, and including at least one of a data signal line, a control voltage line, or a power supply line.
2. The semiconductor device according to claim 1 , wherein the bonding pad and the wiring are provided in a same wiring layer provided above the second semiconductor substrate.
3. The semiconductor device according to claim 1 , further comprising: an insulating film provided over the wiring and includes an opening to expose at least a portion of an upper surface of the bonding pad.
4. The semiconductor device according to claim 1 , wherein the memory cell is provided above the logic circuit.
5. The semiconductor device according to claim 1 , wherein the wiring is configured to at least one of: transmit an input signal to the semiconductor device or an output signal from the semiconductor device, supply a control voltage to the memory cell array, or supply power to the semiconductor device.
6. The semiconductor device according to claim 1 , wherein the wiring is not in contact with the bonding pad.
7. The semiconductor device according to claim 1 , wherein the wiring is in contact with the bonding pad.
8. A method of manufacturing a semiconductor device, comprising:
forming a first chip including:
providing a first semiconductor substrate;
forming a logic circuit on the first semiconductor substrate; and
forming a plurality of bonding metals on a bonding surface of the first chip;
forming a second chip including:
providing a second semiconductor substrate having a first surface and a second surface;
forming a memory cell array on the first surface of the second semiconductor substrate;
forming a plurality of bonding metals on a bonding surface of the second chip; and
forming a plurality of plugs extending through the second semiconductor substrate;
forming a bonding pad on the second surface of the second semiconductor substrate that is electrically connected to the logic circuit via first ones of bonding metals on the bonding surfaces of the first and second chips and a first plug of the plurality of plugs; and
forming a wiring on the second surface of the second semiconductor substrate, electrically connected to the logic circuit via second ones of bonding metals on the bonding surfaces of the first and second chips and a second plug of the plurality of plugs, and including at least one of a data signal line, a control voltage line, or a power supply line.
9. The method of manufacturing a semiconductor device according to claim 8 , further comprising:
forming a wiring layer on the second surface of the second semiconductor substrate; and
processing the wiring layer to form the bonding pad and the wiring.
10. The method of manufacturing a semiconductor device according to claim 8 , further comprising:
bonding the first semiconductor substrate and the second semiconductor substrate via the memory cell array and the logic circuit.
11. A semiconductor device, comprising:
a first chip including a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate;
a second chip bonded on the first chip, the second chip including (i) a second semiconductor substrate having a first surface and a second surface, and (ii) a memory cell array provided on the first surface of the second semiconductor substrate and coupled to the logic circuit through one or more conductive structures;
a plurality of bonding metals provided on a bonding surface of the first chip and the second chip;
a plurality of plugs extending through the second semiconductor substrate;
a bonding pad, provided on the second surface of the second semiconductor substrate, that is electrically connected to the logic circuit via a first bonding metal of the plurality of bonding metals and a first plug of the plurality of plugs; and
a wiring provided on the second surface of the second semiconductor substrate, electrically connected to the logic circuit via a second bonding metal of the plurality of bonding metals and a second plug of the plurality of plugs, and including at least one of a data signal line, a control voltage line, or a power supply line.
12. The semiconductor device of claim 11 , wherein the wiring is not in contact with the bonding pad.
13. The semiconductor device of claim 11 , wherein the wiring is in contact with the bonding pad.
14. The semiconductor device of claim 11 , wherein the bonding pad and the wiring are provided in a same wiring layer provided on the second surface of the second semiconductor substrate.