Transistors including two-dimensional materials

1. A transistor, comprising:

a 2D material structure conformally extending on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, the 2D material structure comprising:

a source region;

a drain region;

a channel region positioned between the source region and the drain region in the first horizontal direction; and

lateral double-diffused regions positioned between the channel region and each of the source region and the drain region in the first horizontal direction; and

a gate structure overlying the channel region of the 2D material structure and extending in a second horizontal direction orthogonal to the first horizontal direction, the gate structure within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction.

2. The transistor of claim 1 , wherein the 2D material structure comprises one or more of WS 2 , WSe 2 , MoS 2 , and MoSe 2 .

3. The transistor of claim 1 , wherein the source region and the drain region of the 2D material structure are doped with at least one N-type dopant.

4. The transistor of claim 1 , wherein the source region and the drain region of the 2D material structure are doped with at least one P-type dopant.

5. The transistor of claim 1 , wherein the source region and the drain region of the 2D material structure are substantially undoped.

6. The transistor of claim 1 , wherein:

the dielectric fin structures each individually exhibit an aspect ratio within a range of from about 0.1:1 to about 10:1; and

a ratio of a width of each of the dielectric fin structures to a distance between horizontally neighboring dielectric structures is within a range of from about 0.1:1 to about 10:1.

7. The transistor of claim 1 , further comprising conductive structures downwardly vertically extending from the gate structure and alternating with the dielectric fin structures in the second horizontal direction.

8. The transistor of claim 1 , further comprising a gate dielectric material interposed between the 2D material structure and each of the gate structure and conductive structures.

9. The transistor of claim 8 , wherein a thickness of the gate dielectric material is within a range of from about 5 nm to about 10 nm.

10. The transistor of claim 1 , wherein:

an electron mobility of the 2D material structure within a range of from about 150 cm 2 /V·s to about 200 cm 2 /V·s; and

a bandgap of the 2D material structure is within a range of from about 1.8 eV to about 2.5 eV.

11. The transistor of claim 1 , wherein the 2D material structure comprises one or more of a transition metal di-chalcogenide, a carbide, a carbonitride, graphene, graphene-oxide, stanine, phosphorene, hexagonal boron nitride, borophene, silicene, graphyne, germanene, germanane, a 2D supracrystal, and a monolayer of a semiconductive material.

12. The transistor of claim 1 , wherein the 2D material structure comprises a transition metal di-chalcogenide having the general chemical formula MX 2 , wherein M is selected from Mo, W, Nb, Zr, Hf, Re, Pt, Ti, Ta, V, Co, Cd, Cr, and wherein X is selected from S, Se, and Te.

13. The transistor of claim 1 , wherein the 2D material structure comprises a carbide or carbonitride having the general chemical formula M n+1 X n , wherein M is selected from Ti, Hf, Zr, V, Nb, Ta, and wherein X is selected from C and N.

14. A transistor, comprising:

a 2D material structure conformally extending on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, the 2D material structure comprising:

a source region;

a drain region; and

a channel region positioned between the source region and the drain region in the first horizontal direction;

a gate structure overlying the channel region of the 2D material structure and extending in a second horizontal direction orthogonal to the first horizontal direction, the gate structure within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction; and

conductive structures vertically extending from the gate structure toward the channel region of the 2D material structure, the conductive structures interposed between the dielectric fin structures in the second horizontal direction.

15. The transistor of claim 14 , further comprising a gate dielectric material interposed between the 2D material structure and each of the gate structure and the conductive structures.

16. The transistor of claim 14 , wherein each of the dielectric fin structures comprises aluminum oxide.

17. The transistor of claim 16 , wherein each of the dielectric fin structures has a hexagonal crystal structure or a rhombohedral crystal structure.

18. The transistor of claim 14 , wherein the 2D material structure has electron mobility within a range of from about 10 cm 2 /V·s to about 400 cm 2 /V·s.

19. The transistor of claim 18 , wherein the 2D material structure has electron mobility within a range of from about 1.2 eV to about 2.5 eV.

20. The transistor of claim 14 , wherein:

the channel region of the 2D material structure has a first conductive contact on an upper surface through;

the source region of the 2D material structure has a second conductive contact vertically extending therethrough; and

the drain region of the 2D material structure has a third conductive contact vertically extending therethrough.

21. The transistor of claim 14 , wherein a width of each of the conductive structures in the first horizontal direction is substantially equal to a width of the gate structure in the first horizontal direction.