IP Library › Granted Patent US 10,950,640
Granted Patent B2
US 10,950,640 · App. 16/551,114 · Granted Mar 16, 2021

Image sensor

Inventors: Young Gu Jin (Suwon-si, KR); Yong Hun Kwon (Hwaseong-si, KR); Young Chan Kim (Seongnam-si, KR); Sae Young Kim (Yongin-si, KR); Sung Young Seo (Bucheon-si, KR); Moo Sup Lim (Yongin-si, KR); Tae Sub Jung (Hwaseong-si, KR); Sung Ho Choi (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L27/14607H01L27/14605H01L27/14614H01L27/14643H01L27/1463H01L27/14621H01L27/14627
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,950,640
App. No.
16/551,114
Granted
Mar 16, 2021
Kind
B2
Abstract

An image sensor includes a plurality of pixels, at least one of the pixels comprising: a photodiode configured to generate charges in response to light; and a pixel circuit disposed on the substrate, and including a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.

Claims (41)

1. An image sensor comprising a plurality of pixels, at least one of the pixels comprising:

a photodiode configured to generate charges in response to light; and

a pixel circuit comprising a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node,

wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.

2. The image sensor of claim 1 , wherein a gate of the transfer transistor comprises a first gate region protruding toward the storage transistor and a second gate region connected to the first gate region, and

wherein the first gate region is disposed on the boundary region.

3. The image sensor of claim 2 , wherein the first gate region of the transfer transistor is disposed on at least a portion of an active region of the storage transistor.

4. The image sensor of claim 2 , wherein a width of the first gate region is smaller than a width of the second gate region in the transfer transistor.

5. The image sensor of claim 2 , wherein a gate of the storage transistor provides a space receiving the first gate region of the transfer transistor.

6. The image sensor of claim 5 , wherein an active region of the storage transistor comprises:

a first impurity region adjacent to the first gate region, and

a second impurity region having an impurity concentration lower than an impurity concentration of the first impurity region.

7. The image sensor of claim 6 , wherein the first impurity region is surrounded by the second impurity region in the storage transistor.

8. The image sensor of claim 6 , wherein at least a portion of the first impurity region of the storage transistor is disposed below the first gate region of the transfer transistor.

9. The image sensor of claim 1 , wherein an active region of the storage transistor comprises:

a first impurity region adjacent to a gate of the transfer transistor, and

a second impurity region having an impurity concentration lower than an impurity concentration of the first impurity region, and

the first impurity region is disposed on the boundary region.

10. The image sensor of claim 9 , wherein an area of the first impurity region is smaller than an area of the second impurity region in the storage transistor.

11. The image sensor of claim 9 , wherein the pixel circuit further comprises an intermediate transfer transistor connected between the photodiode and the storage transistor, and

wherein an active region of the intermediate transfer transistor comprises a third impurity region adjacent to the storage transistor, and a fourth impurity region having an impurity concentration lower than an impurity concentration of the third impurity region.

12. The image sensor of claim 9 , wherein the pixel circuit further comprises an overflow transistor connected between the photodiode and a first power supply node, and

wherein an active region of the overflow transistor comprises a fifth impurity region adjacent to the first power supply node, and a sixth impurity region having an impurity concentration lower than an impurity concentration of the fifth impurity region.

13. The image sensor of claim 1 , wherein each of the pixels comprises the pixel circuit comprising the storage transistor and the transfer transistor, and

wherein the pixels share the photodiode.

14. The image sensor of claim 13 , wherein at least one of the pixels comprises a transfer gate comprising a first gate region protruding toward the storage transistor and a second gate region connected to the first gate region.

15. The image sensor of claim 13 , wherein at least one of the pixels comprises a first impurity region adjacent to the transfer transistor and a second impurity region having an impurity concentration lower than an impurity concentration of the first impurity region.

16. The image sensor of claim 1 , further comprising:

a barrier layer disposed below an active region of the storage transistor.

17. An image sensor comprising a plurality of pixels, at least one of the pixels comprising:

a photodiode configured to generate charges in response to light; and

a pixel circuit comprising a storage transistor connected to the photodiode and a transfer transistor connected between the storage transistor and a floating diffusion node,

wherein, in the pixel circuit, a potential is gradually decreased between the transfer transistor and the storage transistor in a direction away from the storage transistor when the transfer transistor is turned on.

18. The image sensor of claim 17 , wherein a gate of the storage transistor comprises a concave portion, and

wherein a gate of the transfer transistor comprises a convex portion corresponding to the concave portion.

19. The image sensor of claim 18 , wherein when the transfer transistor is turned on, the potential is gradually decreased below the concave portion and the convex portion in the direction away from the storage transistor.

20. An image sensor comprising a plurality of pixels, at least one of the pixels comprising:

a photodiode configured to generate charges in response to light; and

a pixel circuit comprising a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node,

wherein an active region of the storage transistor comprises a first impurity region and a second impurity region having an impurity concentration lower than an impurity concentration of the first impurity region, and

wherein the second impurity region and the first impurity region are sequentially disposed according to a transfer direction of the charges, the first impurity region being disposed closer to the transfer transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2019
From: JIN, YOUNG GU; KWON, YONG HUN; KIM, YOUNG CHAN; KIM, SAE YOUNG; SEO, SUNG YOUNG; LIM, MOO SUP; JUNG, TAE SUB; CHOI, SUNG HO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 050169/0403 →
Priority Claims (1)
KR 10-2019-0025715 · Mar 6, 2019 · national
Continuity (1)
Related Publication 20200286938A1 · Sep 10, 2020
Cited By (1)
US 12,407,957