IP Library › Granted Patent US 11,222,951
Granted Patent B2
US 11,222,951 · App. 16/551,546 · Granted Jan 11, 2022

Epitaxial source/drain structure and method

Inventors: I-Wen Wu (Hsinchu, TW); Chen-Ming Lee (Taoyuan County, TW); Fu-Kai Yang (Hsinchu, TW); Mei-Yun Wang (Hsin-Chu, TW); Chun-An Lin (Tainan, TW); Wei-Yuan Lu (Taipei, TW); Guan-Ren Wang (Hsinchu, TW); Peng Wang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/0847H01L21/02532H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,222,951
App. No.
16/551,546
Granted
Jan 11, 2022
Kind
B2
Abstract

A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Claims (50)

1. A method of semiconductor fabrication, comprising:

providing a semiconductor structure having:

a substrate; and

first, second, third, and fourth fins above the substrate;

forming an n-type epitaxial source/drain (S/D) feature on the first and second fins; and

forming a p-type epitaxial S/D feature on the third and fourth fins; and

performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

2. The method of claim 1 , wherein the selective etch process includes a plurality of cycles, wherein each cycle comprises:

performing a first dry etch process on the semiconductor structure using a first etchant gas;

performing a second dry etch process on the semiconductor structure using a second etchant gas different from the first etchant gas; and

performing a wet clean process to remove a polymer layer that has been formed in the first dry etch process.

3. The method of claim 2 , wherein the first etchant gas is a gas mixture that includes fluoromethane (CH 3 F), hydrogen (H 2 ), and carbonyl sulfide (COS), wherein the gas mixture reacts with silicon germanium in the p-type epitaxial S/D feature in the first dry etch process, thereby forming the polymer layer that includes silicon sulfide.

4. The method of claim 3 , wherein the first dry etch process removes a first thickness of the n-type epitaxial S/D feature, wherein the first dry etch process removes a second thickness of the p-type epitaxial S/D feature that is less than the first thickness due to presence of the polymer layer on the p-type epitaxial S/D feature, and wherein the first dry etch process also forms carbon fluoride (C x F y ) as a byproduct on both the n-type epitaxial S/D feature and the p-type epitaxial S/D feature.

5. The method of claim 4 , wherein the second etchant gas includes diazene (N 2 H 2 ) configured to remove the carbon fluoride formed in the first dry etch process.

6. The method of claim 3 , wherein the wet clean process removes, from the p-type epitaxial S/D feature, silicon sulfide that has been formed in the first dry etch process of each cycle.

7. The method of claim 2 , wherein the plurality of cycles of the selective etch process are conducted at temperatures between 20-60 degrees Celsius and pressures between 10-30 millitorr.

8. The method of claim 2 , wherein, during each cycle of the selective etch process, a first thickness of the n-type epitaxial S/D feature is at least 1 nm thicker than a second thickness of the p-type epitaxial S/D feature.

9. The method of claim 1 , wherein the removed portion of the n-type epitaxial S/D feature is between about 1.5 to about 2.5 times in thickness of the removed portion of the p-type epitaxial S/D feature.

10. The method of claim 1 , wherein the n-type epitaxial S/D feature is formed to include silicon doped with phosphorous but does not include silicon germanium, and wherein the p-type epitaxial S/D feature is formed to include silicon germanium.

11. A method, comprising:

providing a semiconductor structure having a substrate and first and second fins above the substrate;

removing upper portions of the first and second fins while keeping lower portions of the first and second fins;

growing first and second epitaxial source/drain (S/D) features on the lower portions of the first and second fins such that the first and second epitaxial S/D features merge, thereby forming a merged S/D feature with a controllable merge height, wherein the merged S/D feature includes:

a first layer of semiconductor material (L 1 ) grown on the lower portions of the first and second fins;

a second layer of semiconductor material (L 2 - 1 ) grown on the L 1 ; and

a third layer of semiconductor material (L 2 - 2 ) grown on the L 2 - 1 , wherein the L 2 - 2 has a substantially conformal thickness over the first and second fins;

after forming the merged S/D feature, etching the merged S/D feature to thereby form a recessed trench in the merged S/D feature; and

filling into the recessed trench an S/D contact that is in electrical contact with the merged S/D feature.

12. The method of claim 11 , wherein a height of the remaining lower portions of the first and second fins is between about 30% and about 40% of a height of the first and second fins.

13. The method of claim 11 , wherein the L 1 on the first fin and the L 1 on the second fin do not merge, wherein the L 2 - 1 on the first fin and the L 2 - 1 on the second fin merge at the controllable merge height.

14. The method of claim 13 , wherein the controllable merge height is dependent on a ratio between silane (SiH 4 ) and dichlorosilane (DCS) gases which are used to form the L 2 - 1 .

15. The method of claim 14 , wherein the controllable MH is at a position equal to or higher than about 55% of the height of the first and second fins.

16. The method of claim 11 , wherein forming the recessed trench comprises:

etching the merged S/D feature to form an intermediate trench;

depositing a silicon nitride spacer feature in and over the intermediate trench;

removing a bottom portion of the silicon nitride spacer feature using anisotropic etching while keeping sidewall portions of the silicon nitride spacer feature; and

further etching the merged S/D feature in the intermediate trench, thereby forming the recessed trench.

17. A method, comprising:

forming first, second, third, and fourth fins protruding from a substrate;

forming an n-type epitaxial source/drain (S/D) feature on the first and second fins; and

forming a first S/D contact on the n-type epitaxial S/D feature;

forming a p-type epitaxial S/D feature on the third and fourth fins;

forming a second S/D contact on the p-type epitaxial S/D feature; and

prior to forming the first and second S/D contacts, performing a selective etch process on the n-type and p-type epitaxial source/drain features to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature,

wherein a bottom surface of the first S/D contact is lower than a bottom surface of the second S/D contact.

18. The method of claim 17 , wherein the n-type epitaxial S/D feature includes silicon doped with phosphorous but does not include silicon germanium, and wherein the p-type epitaxial S/D feature includes silicon germanium.

19. The method of claim 17 , wherein the selective etch process includes:

performing a first dry etch process using a first etchant gas; and

performing a second dry etch process using a second etchant gas different from the first etchant gas.

20. The method of claim 19 , wherein the performing of the first dry etch process forms a polymer layer on the p-type epitaxial S/D feature.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2020
From: WU, I-WEN; LEE, CHEN-MING; YANG, FU-KAI; WANG, MEI-YUN; LIN, CHUN-AN; LU, WEI-YUAN; WANG, GUAN-REN; WANG, PENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054095/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: WU, I-WEN; LEE, CHEN-MING; YANG, FU-KAI; WANG, MEI-YUN; LIN, CHUN-AN; LU, WEI-YUAN; WANG, GUAN-REN; WANG, PENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050795/0423 →
Continuity (2)
Provisional Application 62725713 · Aug 31, 2018
Related Publication 20200075725A1 · Mar 5, 2020