Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

1. A signal transmitting and receiving apparatus, comprising:

a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin;

a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and

an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit,

wherein the signal transmitting and receiving apparatus receives the first signal from outside the signal transmitting and receiving apparatus through the first pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled, and

the first signal is a data signal and the second signal is a read data strobe signal.

2. The signal transmitting and receiving apparatus of claim 1 ,

wherein, when in a first mode in which the first pin does not require the first termination resistance and the second pin does not require the second termination resistance,

the on-die termination control circuit is configured to disable the first on-die termination circuit and the second on-die termination circuit.

3. The signal transmitting and receiving apparatus of claim 2 ,

wherein, when a second mode in which the first pin requires the first termination resistance and the second pin requires the second termination resistance switches to the first mode, the on-die termination control circuit is configured to disable the first on-die termination circuit a predetermined time after the second on-die termination circuit is disabled.

4. The signal transmitting and receiving apparatus of claim 1 ,

wherein, when a first mode in which the first pin does not require the first termination resistance and the second pin does not require the second termination resistance switches to a second mode in which the first pin requires the first termination resistance and the second pin requires the second termination resistance, the on-die termination control circuit is configured to enable the second on-die termination circuit a predetermined time after the first on-die termination circuit is enabled.

5. The signal transmitting and receiving apparatus of claim 1 ,

wherein a time period, during which the first on-die termination circuit is disabled, is included in a time period, during which the second on-die termination circuit is disabled.

6. The signal transmitting and receiving apparatus of claim 5 ,

wherein the signal transmitting and receiving apparatus transmits the first signal through the first pin in the time period, during which the first on-die termination circuit is disabled, and transmits the second signal through the second pin in the time period, during which the second on-die termination circuit is disabled.

7. The signal transmitting and receiving apparatus of claim 6 ,

wherein the signal transmitting and receiving apparatus transmits the second signal through the second pin in the time period, during which the first on-die termination circuit is disabled.

8. A method of operating an apparatus that transmits or receives a first signal through a first pin and a second signal through a second pin, the method comprising:

disabling a first on-die termination circuit and a second on-die termination circuit, the first on-die termination circuit being connected to the first pin, and the second on-die termination circuit being connected to the second pin;

enabling the first on-die termination circuit such that the first on-die termination circuit provides a first termination resistance to a signal line connected to the first pin;

enabling the second on-die termination circuit such that the second on-die termination circuit provides a second termination resistance to a signal line connected to the second pin, wherein the second on-die termination circuit is enabled a period of time after the first on-die termination circuit is enabled; and

receiving the first signal from outside the apparatus through the first pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled, wherein the first signal is a data signal and the second signal is a read data strobe signal.

9. The method of claim 8 ,

wherein the disabling of the first on-die termination circuit and the second on-die termination circuit comprises:

disabling the second on-die termination circuit; and

disabling the first on-die termination circuit after a first time period elapses from when the second on-die termination circuit is disabled.

10. The method of claim 8 , further comprising:

transmitting a first signal through the first pin before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled; and

transmitting a second signal through the second pin before the second on-die termination circuit is enabled after the second on-die termination circuit is disabled.

11. The method of claim 10 ,

wherein the transmitting of the second signal comprises

transmitting the second signal through the second pin before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled.

12. A memory device, comprising:

a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin;

a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and

an on-die termination control circuit configured to independently control an enable timing or a disable timing of the first on-die termination circuit and an enable timing or a disable timing of the second on-die termination circuit,

wherein the memory device receives the data signal from outside the memory device through the data pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled.

13. The memory device of claim 12 ,

wherein the on-die termination control circuit

is configured to disable the second on-die termination circuit after a first time period elapses since the memory device received a data read command and disable the first on-die termination circuit after a second time period elapses since the memory device received the data read command, the second time period being greater than the first time period.

14. The memory device of claim 13 ,

wherein the on-die termination control circuit

is configured to enable the first on-die termination circuit after a third time period elapses since the memory device received the data read command and enable the second on-die termination circuit after a fourth time period elapses since the memory device received the data read command, the fourth time period being greater than the third time period.

15. The memory device of claim 12 ,

wherein the memory device transmits the data signal outside the memory device through the data pin and transmits the read data strobe signal outside the memory device through the read data strobe pin, before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled.

16. The memory device of claim 12 ,

further comprising a data clock signal pin for receiving a data clock signal from outside the memory device,

wherein the read data strobe pin is configured to output, as the read data strobe signal, a signal synchronized with the data clock signal in a read operation of the memory device.

17. The memory device of claim 12 ,

wherein the memory device provides an indicator signal outside the memory device through a mode register, the indicator signal indicating that the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit.