Multiple semiconductor elements with different threshold voltages

1. A semiconductor device, comprising:

a substrate comprising an array region and a peripheral region surrounding the array region;

a plurality of capacitor structures positioned above the array region of the substrate, wherein the plurality of capacitor structures comprise a plurality of capacitor bottom electrodes inwardly positioned in an insulating film above the array region of the substrate, a capacitor insulating layer inwardly positioned in the plurality of capacitor bottom electrodes, and a capacitor top electrode inwardly positioned in the capacitor insulating layer;

a plurality of bit lines positioned in the array region of the substrate, wherein the plurality of bit lines comprise a plurality of bit line contacts positioned in an upper portion of the array region of the substrate, and top surfaces of the plurality of bit line contacts is at the same vertical level as the top surface of the substrate;

a first semiconductor element positioned above the peripheral region and having a first threshold voltage; and

a second semiconductor element positioned above the peripheral region and having a second threshold voltage;

wherein the first threshold voltage of the first semiconductor element is different from the second threshold voltage of the second semiconductor element.

2. The semiconductor device of claim 1 , wherein the first semiconductor element comprises a first insulating layer and a first bottom conductive layer positioned above the first insulating layer, the second semiconductor element comprises a second insulating layer and a second bottom conductive layer positioned above the second insulating layer, a thickness of the first insulating layer is between about 0.1 nm and about 2.0 nm, and a thickness of the second insulating layer is between about 0.1 nm and about 2.0 nm.

3. The semiconductor device of claim 2 , wherein a thickness of the first bottom conductive layer is between about 1.0 nm and about 3.0 nm, and a thickness of the second bottom conductive layer is between about 1.0 nm and about 3.0 nm.

4. The semiconductor device of claim 3 , wherein the first semiconductor element further comprises a first dipole layer positioned below the first insulating layer, the second semiconductor element further comprises a second dipole layer positioned below the second insulating layer, a thickness of the first dipole layer is between about 0.1 nm and about 1.0 nm, and a thickness of the second dipole layer is between about 0.1 nm and about 1.0 nm.

5. The semiconductor device of claim 4 , wherein the first semiconductor element further comprises a plurality of first spacers, the plurality of first spacers cover sidewalls of the first insulating layer, sidewalls of the first bottom conductive layer, and sidewalls of the first dipole layer, and the plurality of first spacers are formed of an insulating material having a dielectric constant of about 4.0 or greater.

6. The semiconductor device of claim 1 , further comprising an isolation layer positioned in the substrate, wherein the isolation layer is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

7. The semiconductor device of claim 1 , wherein the plurality of bit lines comprise a plurality of bit line bottom electrodes positioned above the plurality of bit line contacts, a plurality of bit line top electrodes positioned above the plurality of bit line bottom electrodes, a plurality of bit line mask patterns positioned above the plurality of bit line top electrodes, and a plurality of bit line spacers covering sidewalls of the plurality of bit line contacts, sidewalls of the plurality of bit line bottom electrodes, sidewalls of the plurality of bit line top electrodes, and sidewalls of the plurality of bit line mask patterns.

8. The semiconductor device of claim 1 , further comprising a plurality of word line insulating layers inwardly positioned in the array region of the substrate, a plurality of word line barrier layers positioned on the plurality of word line insulating layers, a plurality of word line electrodes positioned on the plurality of word line barrier layers, and a plurality of word line capping layers positioned above the plurality of word line barrier layers and the plurality of word line electrodes.