Artificial intelligence accelerator

1. An apparatus, comprising:

a number of memory arrays;

a controller, wherein the controller is configured to:

receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode; and

cause the memory device to perform AI operations using an AI accelerator based on a status of a number of registers; and

cause the memory device to perform the AI operations by locating input data in the number of arrays based on the status of the number of registers and sending the input data to the AI accelerator;

wherein the number of registers define a start address and an end address of a bias value used in the AI operations.

2. The apparatus of claim 1 , wherein the AI accelerator is configured to perform logic operations of the AI operations on the input data.

3. The apparatus of claim 1 , wherein the controller is configured to cause the memory device to store results of the AI operations by locating an output block in the number of arrays based on the status of the number of registers and sending the results of the AI operations to the output block.

4. The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating bias values data in the number of arrays based on the status of the number of registers and sending the bias values to the AI accelerator.

5. The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating activation function data in the number of arrays based on the status of the number of registers and sending the activation function data to the AI accelerator.

6. The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating neural network data in the number of arrays based on the status of the number of registers and sending the neural network data to the AI accelerator.

7. The apparatus of claim 1 , wherein the controller is configured to cause the memory device to perform the AI operations by locating temporary banks in the number of arrays based on the status of the number of registers and sending the data from the AI operations to the temporary banks.

8. The apparatus of claim 1 , wherein the AI accelerator includes an adder/multiplier to perform the AI operations.

9. An apparatus, comprising:

a number of memory arrays;

an artificial intelligence (AI) accelerator, wherein the AI accelerator includes hardware configured to perform AI operations; and

a controller configured to:

receive a command from the host to perform artificial intelligence (AI) operations using the AI accelerator; and

cause execution of the command using the AI accelerator to perform logic operations associated with the AI operations; and

cause the memory device to perform the AI operations by locating input data in the number of arrays based on the status of the number of registers and sending the input data to the AI accelerator;

wherein the AI operations are defined by the number of registers that define the size of a bias value.

10. The apparatus of claim 9 , wherein the command includes the input data that is stored in an input block and used in the AI operations.

11. The apparatus of claim 9 , wherein the controller is configured to cause sending data from an input block and data from a neuron block to the AI accelerator and perform a first step of the AI operations.

12. The apparatus of claim 11 , wherein the controller is configured to cause sending a result of the first step of the AI operations to a temporary block.

13. The apparatus of claim 12 , wherein the controller is configured to cause sending the result of the first step and data from a bias block to the AI accelerator and perform a second step of the AI operations.

14. The apparatus of claim 13 , wherein the controller is configured to cause sending a result of the second step of the AI operations to the temporary block.

15. The apparatus of claim 14 , wherein the controller is configured to cause sending the result of the second step and data from an activation function block to the AI accelerator and perform a third step of the AI operations.

16. The apparatus of claim 15 , wherein the controller is configured to cause sending a result of the third step of the AI operations to an output block.

17. The apparatus of claim 9 , wherein a register is programmed to indicate the AI accelerator is busy.

18. A method, comprising:

performing an artificial intelligence (AI) operation using an AI accelerator on a memory device and data stored on the memory device by locating input data on the memory device based on the status of a first register and sending the input data to the AI accelerator, wherein a second register defines a start address and end address of a bias value used in the AI operation; and

sending a result of the AI operation to a host that requested the AI operation.

19. The method claim 18 , further including performing logic operations of the AI operation using an adder/multiplier on the AI accelerator.

20. The method claim 18 , further including sending neuron information of a neural network to the AI accelerator to perform AI operations.

21. The method claim 18 , further including storing partial results of the AI operation in an array of the memory device.

22. The method claim 18 , further including sending activation function information of a neural network to the AI accelerator to perform AI operations.

23. The method claim 18 , further including sending bias value information of a neural network to the AI accelerator to perform AI operations.