Debug operations on artificial intelligence operations

1. An apparatus, comprising:

a number of memory arrays that are a number of layers of a neural network; and

a controller, wherein the controller is configured to cause the apparatus to:

perform an artificial intelligence (AI) operation on data stored in the number of memory arrays;

perform a debug operation on the AI operation to identify errors of the AI operation;

stop the AI operation in response to performing the debug operation;

store data including the identified errors of the AI operation in a temporary memory block of the number of memory arrays in response to a particular bit of a first register being programmed to a first state;

define, via a second register, a layer of the number of layers of the neural network where errors consistently occur at least partially based on the identified errors;

change the data stored in the temporary memory block to correct the identified errors; and

continue the AI operation using the changed data.

2. The apparatus of claim 1 , wherein the apparatus includes a number of registers.

3. The apparatus of claim 2 , wherein the number of registers include a third register to stop the AI operation.

4. An apparatus, comprising:

a number of memory arrays that are a number of layers of a neural network; and

a controller, wherein the controller is configured to:

receive, from a host, a debug command to perform a debug operation on an artificial intelligence (AI) operation performed on the apparatus;

execute the debug command by causing performance of the debug operation on the AI operation to identify errors of the AI operation;

stop the AI operation in response to executing the debug command;

store data including the identified errors of the AI operation in a temporary memory block of the number of memory arrays in response to a particular bit of a first register being programmed to a first state;

define, via a second register, a layer of the number of layers of the neural network where errors consistently occur at least partially based on the identified errors;

change the data stored in the temporary memory block to correct the identified errors; and

continue the AI operation using the changed data.

5. The apparatus of claim 4 , wherein the AI operation uses input data and neural network data.

6. The apparatus of claim 4 , wherein the AI operation uses partial results of AI operations and bias value data.

7. The apparatus of claim 4 , wherein the AI operation uses partial results of AI operations and activation function data.

8. The apparatus of claim 4 , wherein the temporary memory block is validated.

9. The apparatus of claim 4 , wherein the debug operation includes storing a result of the debug operation in a different temporary memory block of the number of memory arrays.

10. The apparatus of claim 4 , wherein a result of the debug operation is sent to a host.

11. An apparatus, comprising:

a number of memory arrays that are a number of layers of a neural network; and

a controller, wherein the controller is configured to cause the apparatus to:

enable performance of a debug operation on an artificial intelligence (AI) operation to identify errors of the AI operation by writing an indicator in a first register to a particular state in response to receiving a command from a host;

stop the AI operation in response to the performance of the debug operation;

store data including the identified errors of the AI operation in a temporary memory block of the number of memory arrays in response to writing an indicator in a second register to a different particular state;

define, via a third register, a layer of the number of layers of the neural network where errors consistently occur at least partially based on the identified errors;

change the data stored in the temporary memory block to correct the identified errors; and

continue the AI operation using the changed data.

12. The apparatus of claim 11 , wherein a first bit of the first register is programmed to a first state to start the debug operation.

13. The apparatus of claim 11 , wherein a second bit of the first register is programmed to a first state to indicate the AI operation can step forward to continue the AI operation.

14. The apparatus of claim 11 , wherein a third bit of the first register is programmed to a first state to indicate the temporary block is valid.

15. The apparatus of claim 11 , wherein a fourth bit of the first register is programmed to a first state to store data from the AI operation.

16. The apparatus of claim 11 , wherein a fifth bit of the first register is programmed to a first state to send a result of the debug operation to a host.

17. The apparatus of claim 11 , wherein a sixth bit of the first register is programmed to a first state to store a result of the debug operation.

18. A method, comprising:

performing an artificial intelligence (AI) operation on data stored in a number of memory arrays that are a number of layers of a neural network;

performing a debug operation on the AI operation to identify errors of the AI operation;

stopping the AI operation in response to performing the debug operation;

storing data including the identified errors of the AI operation in temporary memory blocks in response to a particular bit of a first register being programmed to a first state;

defining, via a second register, a layer of the number of layers of the neural network where errors consistently occur at least partially based on the identified errors;

changing the data stored in the temporary memory blocks to correct the identified errors; and

continuing the AI operation using the changed data.

19. The method of claim 18 , further comprising updating the neural network based on a result of the debug operation.

20. The method of claim 18 , further updating a bias value based on a result of the debug operation.

21. The method of claim 18 , further comprising updating an activation function based on a result of the debug operation.

22. The method of claim 18 , further comprising updating input data based on a result of the debug operation.