IP Library › Granted Patent US 11,217,699
Granted Patent B2
US 11,217,699 · App. 16/554,723 · Granted Jan 4, 2022

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Hideomi Suzawa (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/4908H01L29/517H01L29/518H01L29/78648
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Quick Facts
Patent No.
US 11,217,699
App. No.
16/554,723
Granted
Jan 4, 2022
Kind
B2
Abstract

A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Claims (85)

1. A semiconductor device comprising:

a first insulating layer;

an oxide semiconductor layer over the first insulating layer;

a second insulating layer over the oxide semiconductor layer, the second insulating layer comprising an opening overlapping with a part of the oxide semiconductor layer;

a third insulating layer covering the opening of the second insulating layer, the third insulating layer being in contact with the part of the oxide semiconductor layer and a side surface of the second insulating layer through the opening of the second insulating layer; and

a gate electrode layer over the third insulating layer, the gate electrode layer overlapping the part of the oxide semiconductor layer, and

wherein the second insulating layer is in contact with the first insulating layer.

2. The semiconductor device according to claim 1 ,

wherein a side surface of the third insulating layer is aligned with a side surface of the gate electrode layer.

3. The semiconductor device according to claim 1 ,

wherein a thickness of the third insulating layer is smaller than a thickness of the second insulating layer.

4. The semiconductor device according to claim 1 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein the first electrode layer has a first thickness, and

wherein an edge of the first electrode layer has a second thickness smaller than the first thickness.

5. The semiconductor device according to claim 1 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein a width of the opening of the second insulating layer in a channel length direction is larger than a distance between the first electrode layer and the second electrode layer.

6. The semiconductor device according to claim 1 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein a width of the opening of the second insulating layer in a channel width direction is smaller than a width of the first electrode layer in the channel width direction.

7. The semiconductor device according to claim 1 ,

wherein the second insulating layer is one selected from the group consisting of a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film and an aluminum nitride oxide film.

8. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor layer includes a first layer and a second layer over and in contact with the first layer, and

wherein an atomic ratio of constituent elements of the first layer is different from an atomic ratio of constituent elements of the second layer.

9. A semiconductor device comprising:

a first insulating layer;

an oxide semiconductor layer over the first insulating layer;

a first electrode layer over and in contact with a first part of the oxide semiconductor layer;

a second electrode layer over and in contact with a second part of the oxide semiconductor layer;

a second insulating layer over the first electrode layer and the second electrode layer, the second insulating layer comprising an opening overlapping with the oxide semiconductor layer;

a third insulating layer covering the opening of the second insulating layer, the third insulating layer being in contact with a third part of the oxide semiconductor layer, an edge of the first electrode layer, an edge of the second electrode layer, and a side surface of the second insulating layer through the opening of the second insulating layer; and

a gate electrode layer over the third insulating layer, the gate electrode layer overlapping the part of the oxide semiconductor layer,

wherein the second insulating layer is in contact with the first insulating layer.

10. The semiconductor device according to claim 9 ,

wherein a side surface of the third insulating layer is aligned with a side surface of the gate electrode layer.

11. The semiconductor device according to claim 9 ,

wherein a thickness of the third insulating layer is smaller than a thickness of the second insulating layer.

12. The semiconductor device according to claim 9 ,

wherein the first electrode layer has a first thickness, and

wherein the edge of the first electrode layer has a second thickness smaller than the first thickness.

13. The semiconductor device according to claim 9 ,

wherein a width of the opening of the second insulating layer in a channel length direction is larger than a distance between the first electrode layer and the second electrode layer.

14. The semiconductor device according to claim 9 ,

wherein a width of the opening of the second insulating layer in a channel width direction is smaller than a width of the first electrode layer in the channel width direction.

15. The semiconductor device according to claim 9 ,

wherein the second insulating layer is one selected from the group consisting of a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film and an aluminum nitride oxide film.

16. A semiconductor device comprising:

a conductive layer;

a first insulating layer over the conductive layer;

an oxide semiconductor layer over the first insulating layer;

a second insulating layer over the oxide semiconductor layer, the second insulating layer comprising an opening overlapping with a part of the oxide semiconductor layer;

a third insulating layer covering the opening of the second insulating layer, the third insulating layer being in contact with the part of the oxide semiconductor layer and a side surface of the second insulating layer through the opening of the second insulating layer; and

a gate electrode layer over the third insulating layer, the gate electrode layer overlapping the part of the oxide semiconductor layer,

wherein the second insulating layer is in contact with the first insulating layer,

wherein the part of the oxide semiconductor layer overlaps the conductive layer.

17. The semiconductor device according to claim 16 ,

wherein a side surface of the third insulating layer is aligned with a side surface of the gate electrode layer.

18. The semiconductor device according to claim 16 ,

wherein a thickness of the third insulating layer is smaller than a thickness of the second insulating layer.

19. The semiconductor device according to claim 16 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein the first electrode layer has a first thickness, and

wherein an edge of the first electrode layer has a second thickness smaller than the first thickness.

20. The semiconductor device according to claim 16 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein a width of the opening of the second insulating layer in a channel length direction is larger than a distance between the first electrode layer and the second electrode layer.

21. The semiconductor device according to claim 16 , further comprising:

a first electrode layer over and in contact with the oxide semiconductor layer; and

a second electrode layer over and in contact with the oxide semiconductor layer,

wherein a width of the opening of the second insulating layer in a channel width direction is smaller than a width of the first electrode layer in the channel width direction.

22. The semiconductor device according to claim 16 ,

wherein the second insulating layer is one selected from the group consisting of a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film and an aluminum nitride oxide film.

23. The semiconductor device according to claim 16 ,

wherein the oxide semiconductor layer includes a first layer and a second layer over and in contact with the first layer, and

wherein an atomic ratio of constituent elements of the first layer is different from an atomic ratio of constituent elements of the second layer.

24. The semiconductor device according to claim 9 ,

wherein the oxide semiconductor layer includes a first layer and a second layer over and in contact with the first layer, and

wherein an atomic ratio of constituent elements of the first layer is different from an atomic ratio of constituent elements of the second layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2019
From: YAMAZAKI, SHUNPEI; SUZAWA, HIDEOMI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 050211/0760 →
Priority Claims (1)
JP 2012-104286 · Apr 30, 2012 · national
Continuity (4)
Continuation 15597237 · May 17, 2017
Continuation 14722260 · May 27, 2015
Continuation 13868420 · Apr 23, 2013
Related Publication 20190386140A1 · Dec 19, 2019
Cited By (1)
US 12,677,446