Adaptable allocation of SRAM based on power

1. A method for processing computer instructions, the method comprising:

receiving, by an instruction dispatch unit of a processor, an instruction that specifies a core instruction state for the instruction, wherein the instruction references low latency data;

storing, by the instruction dispatch unit, the core instruction state into a first selectably-powered portion of an instruction state memory configured to store core instruction state and not low-latency data; and

storing, by the instruction dispatch unit, the low latency data into a row that is already powered on and that includes at least one entry having a type that matches the low latency data, the row being of a second selectably-powered portion of the instruction state memory configured to store low latency data and not core instruction state for instructions.

2. The method of claim 1 , further comprising:

upon receiving high-latency data for the instruction state memory, transmitting, by the instruction dispatch unit, data for the instruction in the instruction state memory and the high-latency data to one or more functional units for execution, wherein the high-latency data has a higher latency of access than low-latency data.

3. The method of claim 2 , further comprising:

determining that, after transmitting the data in the instruction state memory to the one or more functional units for execution, a row from which the data is transmitted has no occupied slots; and

powering down the row.

4. The method of claim 3 , wherein the powering down occurs after a waiting period.

5. The method of claim 1 , further comprising identifying a slot in the instruction state memory for the core instruction state based on clustering criteria, by:

identifying a row in the instruction state memory that has a lowest, non-zero, number of empty slots, out of rows in the instruction state memory; and

identifying, as the slot for the core instruction state, an empty slot of the identified row.

6. The method of claim 1 , wherein:

within the instruction state memory, a first powered-on row includes a first block for data of a first type, wherein the first block is powered on, and a second powered-on row includes a second block for data of the first type, wherein the second block is powered off; and

storing the core instruction state comprises identifying, as the first selectably-powered portion, a slot in the first powered-on row.

7. The method of claim 6 , wherein the second powered-on row includes more empty slots than the first powered-on row.

8. The method of claim 1 , further comprising identifying the first selectably-powered portion by:

determining that no powered-on rows have an empty slot; and

powering on a powered-off row,

wherein the first selectably-powered portion comprises the powered-off row that has been powered on.

9. An instruction state memory of a processor, comprising:

a plurality of selectably powered portions; and

a controller of the processor, the controller configured to:

receive an instruction that specifies a core instruction state for the instruction, wherein the instruction references low latency data;

store the core instruction state into a first selectably-powered portion of the plurality of selectably powered portions configured to store core instruction state for instructions and not low latency data; and

store the low latency data into a row that is already powered on and that includes at least one entry having a type that matches the low latency data, the row being of a second selectably-powered portion of the plurality of selectably powered portions configured to store low latency data and not core instruction state for instructions.

10. The instruction state memory of claim 9 , wherein the controller is further configured to:

upon receiving high-latency data for the instruction state memory, transmit data for the instruction in the instruction state memory and the high-latency data to one or more functional units for execution, wherein the high-latency data has a higher latency of access than low-latency data.

11. The instruction state memory of claim 10 , wherein the controller is further configured to:

determine that, after transmitting the data in the instruction state memory to the one or more functional units for execution, a row from which the data is transmitted has no occupied slots; and

power down the row.

12. The instruction state memory of claim 11 , wherein the powering down occurs after a waiting period.

13. The instruction state memory of claim 9 , wherein the controller is further configured to identifying a slot in the instruction state memory for the core instruction state based on clustering criteria, by:

identifying a row in the instruction state memory that has a lowest, non-zero, number of empty slots, out of rows in the instruction state memory; and

identifying, as the slot for the core instruction state, an empty slot of the identified row.

14. The instruction state memory of claim 9 , wherein:

within the instruction state memory, a first powered-on row includes a first block for data of a first type, wherein the first block is powered on, and a second powered-on row includes a second block for data of the first type, wherein the second block is powered off; and

storing the core instruction state comprises identifying, as the first selectably-powered portion, slot in the first powered-on row.

15. The instruction state memory of claim 14 , wherein the second powered-on row includes more empty slots than the first powered-on row.

16. The instruction state memory of claim 9 , wherein the controller is further configured to identify the first selectably-powered portion by:

determining that no powered-on rows have an empty slot; and

powering on a powered-off row,

wherein the first selectably-powered portion comprises the powered-off row that has been powered on.

17. A processor, comprising:

an instruction state memory, comprising:

a plurality of selectably powered portions; and

a controller configured to:

receive an instruction that specifies a core instruction state identifying one or more micro-operations for the instruction, wherein the instruction references low latency data;

store the core instruction state into a first selectably-powered portion of the plurality of selectably powered portions configured to store core instruction state for instructions and not low latency data; and

store the low latency data into a row that is already powered on and that includes at least one entry having a type that matches the low latency data, the row being of a second selectably-powered portion of the plurality of selectably powered portions configured to store low latency data and not core instruction state for instructions.

18. The processor of claim 17 , wherein the controller is further configured to:

upon receiving high-latency data for the instruction state memory, transmit data for the instruction in the instruction state memory and the high-latency data to one or more functional units for execution, wherein the high-latency data has a higher latency of access than low-latency.

19. The processor of claim 18 , wherein the controller is further configured to:

determine that, after transmitting the data in the instruction state memory to the one or more functional units for execution, a row from which the data is transmitted has no occupied slots; and

power down the row.

20. The processor of claim 19 , wherein the powering down occurs after a waiting period.