IP Library › Granted Patent US 11,004,727
Granted Patent B2
US 11,004,727 · App. 16/556,330 · Granted May 11, 2021

Method for fabricating electrode and semiconductor device

Inventors: Motomu Kurata (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Ryota Hodo (Kanagawa, JP); Yuta Iida (Kanagawa, JP); Satoru Okamoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L21/76802H01L21/76814H01L21/76843H01L21/76855H01L29/78666
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Quick Facts
Patent No.
US 11,004,727
App. No.
16/556,330
Granted
May 11, 2021
Kind
B2
Abstract

A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Claims (38)

1. A method for fabricating a semiconductor device, comprising:

forming a first insulator over a substrate;

forming a first conductor comprising a metal element and a second conductor over the first insulator, wherein the first conductor and the second conductor are formed from a same film;

forming a second insulator over the first conductor and the second conductor;

forming a semiconductor over the second insulator;

forming a third conductor over the semiconductor as a source or drain electrode;

forming a third insulator over the third conductor;

forming a fourth conductor as a first gate electrode over the third insulator;

forming a fourth insulator over the fourth conductor;

forming a mask layer over the fourth insulator;

forming a first opening that reaches a top surface of the first conductor in the second insulator, the third insulator, and the fourth insulator to expose the top surface of the first conductor, wherein the first opening is formed by etching the second insulator, the third insulator, and the fourth insulator using plasma and the mask layer as a mask;

performing plasma treatment on at least the first opening so as to form an oxide comprising the metal element from the first conductor, wherein the plasma treatment is performed in an atmosphere containing oxygen;

removing the oxide; and

forming a fifth conductor in the first opening,

wherein the second conductor comprises a second gate electrode.

2. The method for fabricating the semiconductor device, according to claim 1 ,

wherein the oxide is removed by washing treatment using a liquid in the removing step.

3. The method for fabricating the semiconductor device, according to claim 2 ,

wherein the washing treatment comprises three or more cycles of first to fourth steps,

wherein the first step is to supply water so that a washing bath overflows while bubbling the water in the washing bath with the use of a nitrogen gas,

wherein the second step is to drain the water from the washing bath while supplying water from a shower to the washing bath,

wherein the third step is to supply water in the washing bath, and

wherein the fourth step is to supply water so that the washing bath overflows while bubbling the water in the washing bath with the use of a nitrogen gas.

4. The method for fabricating the semiconductor device, according to claim 1 ,

wherein the first conductor is a conductive layer containing tungsten.

5. The method for fabricating the semiconductor device, according to claim 1 ,

wherein the second conductor and the fourth conductor overlap with each other.

6. The method for fabricating the semiconductor device, according to claim 1 ,

wherein the semiconductor does not overlap with the first conductor.

7. The method for fabricating the semiconductor device, according to claim 1 ,

wherein a second opening is formed in the same step as the step of forming the first opening, and

wherein the second opening is formed in the third insulator and the fourth insulator to expose a top surface of the source or drain electrode.

8. The method for fabricating the semiconductor device, according to claim 1 ,

wherein the source or drain electrode is not overlapped with the first conductor.

9. The method for fabricating the semiconductor device, according to claim 1 , further comprising a step of forming a fifth insulator over the fourth insulator,

wherein the first opening is formed in the fifth insulator.

10. The method for fabricating the semiconductor device, according to claim 9 , further comprising a step of forming a sixth conductor over the fifth insulator,

wherein the sixth conductor is electrically connected to the first conductor through the fifth conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2019
From: KURATA, MOTOMU; SASAGAWA, SHINYA; HODO, RYOTA; IIDA, YUTA; OKAMOTO, SATORU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 050223/0613 →
Priority Claims (1)
JP 2015-083537 · Apr 15, 2015 · national
Continuity (2)
Division 15092973 · Apr 7, 2016
Related Publication 20190393079A1 · Dec 26, 2019
Cited By (1)
US 12,453,187