Software assisted power management

1. An apparatus comprising:

an execution unit coupled to a memory;

a microcode controller to:

identify a global hint in an instruction stream, the instruction stream including a first instruction phase and a second instruction phase to be executed in parallel;

identify a first local hint in the first instruction phase in the instruction stream; and

balance power consumption between the execution unit and the memory during parallel executions of the first instruction phase and the second instruction phase based, at least in part, on the first local hint; and

a hardware controller coupled to the microcode controller, the hardware controller to:

based on the global hint, determine a voltage level of a compute voltage and a frequency of a compute clock signal to be used by the execution unit during the parallel executions of the first instruction phase and the second instruction phase, wherein the first instruction phase includes a matrix multiply compute instruction, and wherein the second instruction phase includes a memory copy instruction.

2. The apparatus of claim 1 , wherein, based on the global hint indicating that the instruction stream is to use more compute resources than memory resources, the hardware controller is to determine that at least one of the frequency of the compute clock signal and the voltage level of the compute voltage for the execution unit is to be increased.

3. The apparatus of claim 2 , wherein the power consumption by the execution unit is to be increased during the parallel executions of the first instruction phase and the second instruction phase by increasing a compute pipeline rate for the first instruction phase based, in part, on the first local hint.

4. The apparatus of claim 2 , wherein the power consumption by the memory is to be decreased during the parallel executions of the first instruction phase and the second instruction phase by decreasing memory access bandwidth of the memory based, in part, on the first local hint.

5. The apparatus of claim 4 , wherein the memory access bandwidth is to be decreased by inserting a number of rate control instructions into the second instruction phase.

6. The apparatus of claim 5 , wherein the number of rate control instructions is selected to synchronize an execution completion of the second instruction phase with an execution completion of the first instruction phase.

7. The apparatus of claim 1 , wherein, based on the global hint indicating that the instruction stream is to use more memory resources than compute resources, the hardware controller is to determine that at least one of the frequency of the compute clock signal and the voltage level of the compute voltage for the execution unit is to be decreased.

8. The apparatus of claim 7 , wherein the power consumption of the memory is to be increased during the parallel executions of the first instruction phase and the second instruction phase by increasing a memory access bandwidth of the memory based, in part, on the first local hint.

9. The apparatus of claim 7 , wherein the power consumption of the execution unit is to be decreased during the parallel executions of the first instruction phase and the second instruction phase by decreasing a compute pipeline rate based, in part, on the first local hint.

10. The apparatus of claim 9 , wherein the compute pipeline rate is to be decreased by inserting a number of rate control instructions into the first instruction phase.

11. The apparatus of claim 10 , wherein the number of rate control instructions is selected to synchronize an execution completion of the second instruction phase with an execution completion of the first instruction phase.

12. The apparatus of claim 1 , wherein the first local hint includes a first processing rate for the first instruction phase or an indication of the first processing rate for the first instruction phase.

13. The apparatus of claim 12 , wherein the first processing rate for the first instruction phase is one of a number of clock cycles to execute the first instruction phase, a percentage of a total time to execute the instruction stream, or an amount of time to execute the first instruction phase.

14. The apparatus of claim 12 , wherein the indication of the first processing rate includes a type of workload of the first instruction phase, and wherein the microcode controller is further to determine the first processing rate for the first instruction phase based on the type of workload of the first instruction phase indicated by the first local hint.

15. The apparatus of claim 14 , wherein the first processing rate for the first instruction phase is preprogrammed in a rate store.

16. The apparatus of claim 1 , wherein the microcode controller is further to:

identify a second local hint in the second instruction phase of the instruction stream;

determine a first processing rate for the first instruction phase based on the first local hint;

determine a second processing rate for the second instruction phase based on the second local hint; and

balance the power consumption between the execution unit and the memory based, in part, on a comparison of the first processing rate and the second processing rate.

17. A system comprising:

a memory;

an execution unit coupled to the memory;

a microcode controller to:

decode a first instruction phase and a second instruction phase in an instruction stream, the first and second instruction phases to be executed in parallel;

identify a first local hint in the first instruction phase;

identify a second local hint in the second instruction phase;

determine a first processing rate for the first instruction phase based on the first local hint;

determine a second processing rate for the second instruction phase based on the second local hint; and

based on determining that the first processing rate for the first instruction phase is greater than the second processing rate for the second instruction phase, insert a number of rate control instructions into the second instruction phase to synchronize execution completion of the second instruction phase with the first instruction phase.

18. The system of claim 17 , wherein the microcode controller is further to identify a global hint in the instruction stream, and wherein the system further comprises a hardware controller to:

determine that at least one of a voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit is to be adjusted based, at least in part, on the global hint.

19. The system of claim 17 , wherein the first local hint includes the first processing rate for the first instruction phase or an indication of the first processing rate for the first instruction phase, and wherein the second local hint includes the second processing rate for the second instruction phase or an indication of the second processing rate for the second instruction phase.

20. A method, the method comprising:

identifying a global hint in an instruction stream, the instruction stream including a compute instruction phase to be executed by an execution unit of a processor core;

decoding the compute instruction phase in the instruction stream;

identifying a first local hint in the compute instruction phase;

determining a processing rate for the compute instruction phase based on the first local hint;

sending the processing rate to the execution unit to increase power consumption by the execution unit by increasing a compute pipeline rate for the compute instruction phase;

based on the global hint, increasing a voltage level of a compute voltage and increasing a frequency of a compute clock signal for the execution unit during an execution of the compute instruction phase;

decoding a memory instruction phase in the instruction stream;

identifying a second local hint in the memory instruction phase in the instruction stream;

identifying a third local hint in a third instruction phase in the instruction stream, the memory instruction phase and the third instruction phase to be executed in parallel; and

balancing power consumption between the execution unit and a memory during parallel executions of the memory instruction phase and the third instruction phase based, at least in part, on the second local hint and the third local hint.

21. An apparatus comprising:

an execution unit coupled to a memory;

a microcode controller to:

identify a global hint in an instruction stream, the instruction stream including a first instruction phase and a second instruction phase to be executed in parallel;

identify a first local hint in the first instruction phase in the instruction stream; and

balance power consumption between the execution unit and the memory during parallel executions of the first instruction phase and the second instruction phase based, at least in part, on the first local hint; and

a hardware controller coupled to the microcode controller, the hardware controller to:

based on the global hint, determine a voltage level of a compute voltage and a frequency of a compute clock signal to be used by the execution unit during the parallel executions of the first instruction phase and the second instruction phase, wherein the first instruction phase includes a memory copy instruction, and wherein the second instruction phase includes a matrix multiply compute instruction.

22. The apparatus of claim 21 , wherein the first local hint includes an indication of a first processing rate for the first instruction phase, and wherein the indication of the first processing rate includes a type of workload of the first instruction phase.