System and method for accelerating timing-accurate gate-level logic simulation
A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.
1. A method of accelerating a timing-accurate gate-level logic simulation, the method comprising:
dividing a design into a plurality of partitions;
for a respective partition of the plurality of partitions with output ports, tracing drivers of all of the output ports at a partition boundary associated with the respective partition until at least one gate terminal is reached, the at least one gate terminal also being a send list for the respective partition;
for each partition of the plurality of partitions with inout ports, selecting a partition for each inout port, said each inout port being in the send list of the selected partition;
tracing drivers of the inout port with the respective partition in all remaining partitions until a second at least one gate terminal is reached, the second at least one gate terminal also being a send list for the respective partition;
identifying a value change associated with the at least one gate terminal, the value change corresponding to a delay;
transmitting the identified value change to at least one partition of the plurality of partitions;
forcing all inputs of blocks not to be simulated in a partition, or all loads of terminals in the send list, to a predetermined constant value;
conducting a parallel simulation;
monitoring at least one upstream flip flop (FF) that drives send list terminals during the parallel simulation; and
skipping a synchronization point for a current cycle if at least a value associated with the at least one upstream FF exhibits no change during the monitoring.
2. The method of claim 1 , wherein the plurality of partitions are divided along block boundaries.
3. The method of claim 1 , wherein delays between signals in the send list and their downstream logic are preserved.
4. The method of claim 1 , wherein at least one partition of the plurality of partitions have a testbench.
5. The method of claim 4 , wherein the at least one partition having the testbench comprises at least a portion of a design under test (DUT).
6. The method of claim 4 , wherein at least one partition of the plurality of partitions do not include a testbench.
7. A system for accelerating a timing-accurate gate-level logic simulation, the system comprising:
a memory having program instructions stored thereon; and
a processor configured to:
divide a design into a plurality of partitions;
for a respective partition of the plurality of partitions with output ports, trace drivers of all of the output ports at a partition boundary associated with the respective partition until at least one gate terminal is reached, the at least one gate terminal being a send list for the respective partition;
for each partition of the plurality of partitions with inout ports, select a partition for each inout port, said each inout port being in the send list of the selected partition;
trace drivers of the inout port with the respective partition in all remaining partitions until a second at least one gate terminal is reached, the second at least one gate terminal also being a send list for the respective partition;
identify a value change associated with the at least one gate terminal, the value change corresponding to a delay;
transmit the identified value change to at least one partition of the plurality of partitions;
force all inputs of blocks not to be simulated in a partition, or all loads of terminals in the send list, to a predetermined constant value;
conduct a parallel simulation;
monitor at least one upstream flip flop (FF) that drives send list terminals during the parallel simulation; and
skip a synchronization point for a current cycle if at least a value associated with the at least one upstream FF exhibits no change during the monitoring.
8. The system of claim 7 , wherein the plurality of partitions are divided along block boundaries.
9. The system of claim 7 , wherein delays between signals in the send list and their downstream logic are preserved.
10. The system of claim 7 , wherein at least one partition of the plurality of partitions have a testbench.
11. The system of claim 10 , wherein the at least one partition having the testbench comprises at least a portion of a design under test (DUT).
12. The system of claim 10 , wherein at least one partition of the plurality of partitions do not include a testbench.
13. A non-transitory computer readable medium containing program instructions for causing a computer to perform a method of:
dividing a design into a plurality of partitions;
for a respective partition of the plurality of partitions with output ports, tracing drivers of all of the output ports at a partition boundary associated with the respective partition until at least one gate terminal is reached, the at least one gate terminal also being a send list for the respective partition;
for each partition of the plurality of partitions with inout ports, selecting a partition for each inout port, each said inout port being in the send list of the selected partition;
tracing drivers of the inout port with the respective partition in all remaining partitions until a second at least one gate terminal is reached, the second at least one gate terminal also being a send list for the respective partition;
identifying a value change associated with the at least one gate terminal, the value change corresponding to a delay;
transmitting the identified value change to at least one partition of the plurality of partitions;
forcing all inputs of blocks not to be simulated in a partition, or all loads of terminals in the send list, to a predetermined constant value;
conducting a parallel simulation;
monitoring at least one upstream flip flop (FF) that drives send list terminals during the parallel simulation; and
skipping a synchronization point for a current cycle if at least a value associated with the at least one upstream FF exhibits no change during the monitoring.
14. The non-transitory computer readable medium of claim 13 , wherein the plurality of partitions are divided along block boundaries.
15. The non-transitory computer readable medium of claim 13 , wherein delays between signals in the send list and their downstream logic are preserved.
16. The non-transitory computer readable medium of claim 13 , wherein at least one partition of the plurality of partitions have a testbench.
17. The non-transitory computer readable medium of claim 16 , wherein the at least one partition having the testbench comprises at least a portion of a design under test (DUT).
18. The non-transitory computer readable medium of claim 16 , wherein at least one partition of the plurality of partitions do not include a testbench.