Event-driven design simulation
A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
1. A method comprising:
receiving a specification of a digital circuit, the specification comprising a plurality of instructions for modeling behaviors of the digital circuit, each instruction specifying an operation and a set of fan-out destinations;
storing each instruction at a corresponding respective memory location in an instruction memory;
executing the plurality of instructions, wherein executing an instruction comprises:
(i) generating an instruction address;
(ii) using the generated instruction address to fetch the instruction from the instruction memory and to fetch the instruction's input data from a data memory;
(iii) performing the operation specified by the fetched instruction based on the fetched input data and producing an output data of the instruction; and
(iv) storing the output data in a set of memory locations of the data memory according to the set of fan-out destinations specified by the instruction.
2. The method of claim 1 , wherein the instruction memory and the data memory are part of a same memory structure, wherein the instruction and the instruction's inputs are stored in a same memory location that is addressed by the same generated instruction address.
3. The method of claim 1 further comprising generating simulation data based on the output data of each instruction stored in the data memory at different simulation time steps.
4. The method of claim 1 , wherein the set of fan-out destinations specifies at least one destination instruction in the plurality of instructions.
5. The method of claim 4 , wherein the output data of the executed instruction is stored in the data memory to serve as input data for the destination instruction, wherein the output data is stored at a location in the data memory that has the same address as the destination instruction in the instruction memory.
6. The method of claim 1 , wherein the plurality of instructions are divided into a plurality of groups of instructions, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group.
7. The method of claim 6 , wherein executing the plurality of instructions comprises selecting a group of instructions and executing the selected group of instructions.
8. An integrated circuit (IC) comprising:
an instruction memory;
a data memory;
a set of processing units configured to execute a plurality of instructions stored in the instruction memory and produce output data, each instruction specifying an operation and a set of fan-out destinations;
a fetching circuit configured to fetch each instruction and its corresponding input data, wherein each instruction is stored in the instruction memory at a same address location as the instruction's input data in the data memory;
a data access circuit configured to store the output data of each instruction at a set of destination locations in the data memory according to the instruction's set of fan-out destinations.
9. The IC of claim 8 , wherein the instruction memory and the data memory are part of a same memory structure, wherein the instruction and the instruction's inputs are stored in a same memory location that is addressed by the same generated instruction address.
10. The IC of claim 8 , wherein the data access circuit is further configured to generate simulation data based on the output data of each instruction stored in the data memory at different simulation time steps.
11. The IC of claim 8 , wherein the set of fan-out destinations specifies at least one destination instruction in the plurality of instructions.
12. The IC of claim 11 , wherein data access circuit stores the output data of the executed instruction in the data memory to serve as input data for the destination instruction, wherein the output data is stored at a location in the data memory that has the same address as the destination instruction in the instruction memory.
13. The IC of claim 8 , wherein the plurality of instructions are sorted into a plurality of groups of instructions, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group.
14. The IC of claim 13 , wherein the fetching circuit is further configured to select a group of instructions for execution by the set of processing units.
15. A simulation system comprising:
a simulation processor configured to execute a set of compiled models to generate stimulus for testing a design of a digital circuit; and
a simulation accelerator configured to perform acts comprising:
receiving a plurality of instructions emulating a behavior of the digital circuit, each instruction specifying an operation and a set of fan-out destinations,
storing each instruction at a corresponding respective memory location in an instruction memory;
executing the plurality of instructions, wherein executing an instruction comprises:
(i) generating an instruction address;
(ii) using the generated instruction address to fetch the instruction from the instruction memory and to fetch the instruction's input data from a data memory;
(iii) performing the operation specified by the fetched instruction based on the fetched input data by applying the generated stimulus, and producing an output data of the instruction; and
(iv) storing the output data in a set of memory locations of the data memory according to the set of fan-out destinations specified by the instruction.
16. The simulation system of claim 15 , wherein the instruction memory and the data memory are part of a same memory structure, wherein the instruction and the instruction's inputs are stored in a same memory location that is addressed by the same generated instruction address.
17. The simulation system of claim 15 , wherein the simulation accelerator is further configured to generate simulation data based on the output data of each instruction stored in the data memory at different simulation time steps.
18. The simulation system of claim 15 , wherein the set of fan-out destinations specifies at least one destination instruction in the plurality of instructions.
19. The simulation system of claim 18 , wherein the output data of the executed instruction is stored in the data memory to serve as input data for the destination instruction, wherein the output data is stored at a location in the data memory that has the same address as the destination instruction in the instruction memory.
20. The simulation of claim 15 , wherein the plurality of instructions are sorted into a plurality of groups of instructions, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group, wherein the accelerator executes the plurality of instructions by selecting a group of instructions and executing the selected group of instructions.