Information sending and receiving method and related device
Embodiments of this application disclose an information sending and receiving method and a related device. The method may include: sending, by a network device, first indication information to a terminal device, where the first indication information is carried by using m bits in a downlink signal, and the first indication information includes related information indicating a quantity n of synchronization signal blocks SS blocks included in a synchronization signal burst set SS burst set, where m<log 2 N, N is a maximum value of a quantity of SS blocks supported in the SS burst set, both m and n are integers greater than 1 , and n is less than or equal to N. According to the embodiments of this application, a prior-art problem that transmission overheads are relatively high when the network device indicates the quantity n of SS blocks to the terminal device can be resolved.
1. An information sending method, wherein the method comprises:
enabling, by a network device, a physical broadcast channel (PBCH) to carry Q bits that are used to indicate a synchronization signal (SS) block time index, the SS block time index comprising M bits, (M−Q) bits of the M bits being implicitly carried by using demodulation reference signal (DMRS) sequences of the PBCH, M being a first integer greater than 0, and Q being a second integer greater than 0; and
sending the PBCH to a terminal device.
2. The method according to claim 1 , wherein the Q bits are explicitly carried on the PBCH.
3. The method according to claim 1 , wherein the (M−Q) bits of the M bits correspond to one of eight different DMRS sequences.
4. The method according to claim 1 , wherein a value of M is associated with a quantity of SS blocks sent in an SS burst set.
5. The method according to claim 1 , wherein a value of M is associated with a maximum quantity of SS block supported by a different carrier band.
6. The method according to claim 1 , wherein Q is 3, and M is 6.
7. An information receiving method, wherein the method comprises:
receiving, by a terminal, a physical broadcast channel (PBCH); and
obtaining, by the terminal, a synchronization signal (SS) block time index, the SS block time index comprising M bits, Q bits of the M bits used to indicate the SS block time index being carried on the PBCH, and (M−Q) bits of the M bits being implicitly carried by using demodulation reference signal (DMRS) sequences of the PBCH, M being a first integer greater than 0, and Q being a second integer greater than 0.
8. The method according to claim 7 , wherein the Q bits are explicitly carried on the PBCH.
9. The method according to claim 7 , wherein the (M−Q) bits of the M bits correspond to one of eight DMRS sequences.
10. The method according to claim 7 , wherein a value of M is associated with a quantity of SS blocks sent in an SS burst set.
11. The method according to claim 7 , wherein a value of M is associated with a maximum quantity of SS blocks supported by a different carrier band.
12. The method according to claim 7 , wherein Q is 3, and M is 6.
13. The method according to claim 7 , wherein the obtaining the information about the SS block time index comprises:
detecting, by the terminal, the PBCH and obtaining a data bits width of the PBCH; and
obtaining, by the terminal, the SS block time index according to the data bits width of the PBCH.
14. The method according to claim 7 , wherein the DMRS of the PBCH is scrambled by a tertiary sequence (TSS).
15. The method according to claim 7 , wherein the PBCH further comprises 1 bit indicating whether the (M−Q) bits need to be solved.
16. A apparatus, comprising:
one or more memories configured to store instructions; and
one or more processors coupled to the one or more memories and configured to execute the instructions to cause the apparatus to:
enable a physical broadcast channel (PBCH) to carry Q bits that are used to indicate a synchronization signal (SS) block time index, wherein the SS block time index comprises M bits, wherein (M−Q) bits of the M bits are implicitly carried by using demodulation reference signal (DMRS) sequences of the PBCH, and wherein M is a first integer greater than 0, and Q is a second integer greater than 0; and
a communications unit, configured to send the PBCH to a terminal.
17. The apparatus according to claim 16 , wherein the Q bits are explicitly carried on the PBCH.
18. The apparatus according to claim 16 , wherein the (M−Q) bits correspond to one of eight different DMRS sequences.
19. The apparatus according to claim 16 , wherein a value of M is associated with a quantity of SS blocks sent in an SS burst set.
20. The apparatus according to claim 16 , wherein a value of M is associated with a maximum quantity of SS blocks supported by a different carrier band.
21. The apparatus according to claim 16 , wherein Q is 3, and M is 6.
22. A apparatus, comprising:
one or more memories configured to store instructions; and
one or more processors coupled to the one or more memories and configured to execute the instructions to cause the apparatus to:
receive a physical broadcast channel (PBCH);
detect the PBCH; and
obtain information about a synchronization signal (SS) block time index, wherein the SS block time index comprises M bits, wherein Q bits of the M bits that are used to indicate the SS block time index are carried on the PBCH, wherein (M−Q) bits of the M bits are implicitly carried by using different demodulation reference signal (DMRS) sequences of the PBCH, and wherein M is a first integer greater than 0, and Q is second integer greater than 0.
23. The apparatus according to claim 22 , wherein the Q bits are explicitly carried on the PBCH.
24. The apparatus according to claim 22 , wherein the (M−Q) bits correspond to one of eight different DMRS sequences.
25. The apparatus according to claim 22 , wherein a value of M is associated with a quantity of SS blocks actually sent in an SS burst set.
26. The apparatus according to claim 22 , wherein a value of M is associated with a maximum quantity of SS blocks supported by a different carrier band.
27. The apparatus according to claim 22 , wherein Q is 3, and M is 6.
28. The apparatus according to claim 22 , wherein the one or more processors are configured to execute the instructions to cause the apparatus to:
detect the PBCH and obtain a data bits width of the PBCH; and
obtain the SS block time index according to the data bits width of the PBCH.
29. The apparatus according to claim 22 , wherein the DMRS of the PBCH is scrambled by a tertiary sequence (TSS).
30. The apparatus according to claim 22 , wherein the PBCH further comprises 1 bit indicating whether the (M−Q) bits need to be solved.