Multilayer ceramic capacitor, package of multilayer ceramic capacitor and component mounting circuit substrate
A ceramic electronic device includes: a multilayer chip having a first and a second internal electrode layers; a first and a second external electrodes covering a first a second regions of a surface of the multilayer chip, wherein: a mark is shifted on a side of one of two end faces on an upper face; the first internal electrode layer is exposed to the first region and connected to the first external electrode; the second internal electrode layer is exposed to the second region and connected to the second external electrode; the second internal electrode is shifted further on a side of the lower face than on a side of the upper face; the second internal electrode layer is shifted further on a side of the lower face than the upper face; the second region is a region of a half of the surface on the lower face side.
1. A multilayer ceramic capacitor comprising:
a multilayer chip that has a rectangular parallelepiped shape and has two end faces facing with each other, an upper face and a lower face facing with each other, and two side faces facing with each other;
a first external electrode that covers a first region of a surface of the multilayer chip; and
a second external electrode that covers a second region of the surface of the multilayer chip, the second region being different from the first region,
wherein the multilayer chip has a first internal electrode layer and a second internal electrode layer that face with each other and sandwich a dielectric layer of which a main component is ceramic,
wherein the multilayer chip has a mark that is shifted on a side of one of the two end faces on the upper face and has a color different from that of the dielectric layer,
wherein the first internal electrode layer is exposed to the first region and is connected to the first external electrode,
wherein the second internal electrode layer is exposed to the second region and is connected to the second external electrode,
wherein the second internal electrode is shifted further on a side of the lower face than on a side of the upper face,
wherein the second region is a region of a half of the surface of the multilayer chip on the lower face side, in a facing direction of the upper face and the lower face.
2. The multilayer ceramic capacitor as claimed in claim 1 , wherein the first internal electrode layer extends further toward the upper face than the second internal electrode layer extend toward the upper face.
3. The multilayer ceramic capacitor as claimed in claim 1 , wherein the mark is not provided in a plane formed by the first internal electrode layer but is provided in a plane formed by the second internal electrode layer.
4. The multilayer ceramic capacitor as claimed in claim 1 , wherein the first region extends from one of the two end faces to the lower face,
wherein the second region extends from the other of the two end faces to the lower face.
5. The multilayer ceramic capacitor as claimed in claim 1 , wherein the second internal electrode layer is not provided on a region of a half of the multilayer chip on the side of the upper face, but is provided on a region of a half of the multilayer chip on the side of the lower face, in a facing direction of the upper face and the lower face.
6. A package of a multilayer ceramic capacitor comprising:
a plurality of multilayer ceramic capacitors as claimed in claim 1 ; and
a carrier tape that has a plurality of housing parts for housing the plurality of multilayer ceramic capacitors,
wherein each of the plurality of multilayer ceramic capacitors is housed in each of the plurality of housing parts so that the marks of the plurality of multilayer ceramic capacitor are shifted to one of sides of the each of the housing parts.
7. A component mounting circuit substrate comprising:
a substrate having a ground electrode and a signal electrode that are provided on a face thereof; and
a multilayer ceramic capacitor as claimed in claim 1 ,
wherein the first external electrode is connected to the ground electrode,
wherein the second external electrode is connected to the signal electrode.