Memory device with configurable performance and defectivity management

1. A memory device comprising:

a memory array including memory cells;

an interface configured to receive memory access requests; and

a memory control unit operatively coupled to the memory array and the interface, the memory control unit comprising a processor configured to execute instructions stored on the memory device that, when executed by the processor, cause the processor to:

control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including a memory cell defectivity protocol and including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption;

monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption;

determine when a boundary condition for one of the multiple operating conditions is met;

in response to determining that a first boundary for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a changed boundary condition of a second monitored operating condition;

monitor an activation rate at which the memory cell defectivity protocol is activated; and

establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for a memory access request, and an amount of duplicated data written as part of the memory access request in response to a determined memory cell defectivity protocol activation rate.

2. The memory device of claim 1 , wherein the processor is configured to execute instructions that cause the processor to:

monitor a rate of P/E cycles of the memory array performed in response to the memory access requests; and

establish the second memory management protocol by changing an access policy to memory cell cache by the memory access requests according to a determined rate of P/E cycles.

3. The memory device of claim 2 , wherein the processor is configured to execute instructions that cause the processor to: establish the second memory management protocol by reallocating memory cells included in a single level cell (SLC) cache to multiple level cell (MLC) storage according to the determined rate of the P/E cycles.

4. The memory device of claim 1 , wherein the processor is configured to execute instructions that cause the processor to:

monitor operating conditions of the memory array for memory cell endurance; and

establish the second memory management protocol by changing access to a number of single level cells (SLCs) and multiple level cell (MLCs) given to the memory access requests according to a determined operating condition of the memory array for memory cell endurance.

5. The memory device of claim 1 , wherein the processor is configured to execute instructions that cause the processor to:

monitor operating conditions of the memory array for memory cell endurance; and

establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for the memory access request, and an amount of duplicated data written as part of the memory access request according to a determined operating condition of the memory array for memory cell endurance.

6. The memory device of claim 1 , wherein the processor is configured to execute instructions that cause the processor to:

establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection, an amount of duplicated data written to the memory array, a number of parity bits stored, and an access policy to memory cell cache granted to the memory access requests according to a determined operating condition of the memory array for power consumption.

7. A method of operating a memory device, the method comprising:

receiving memory access requests to a memory array of the memory device from a host device;

accessing the memory array of the memory device according to a first memory management protocol, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption;

monitoring operating conditions of the memory array for the P/E cycles, error management operations, DWPD, power consumption, and a level of memory cell defectivity;

determining when a boundary condition for one of the multiple operating conditions is met; and

changing, in response to determining that a first boundary condition for a first monitored operating condition is met, one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a changed boundary condition of a second monitored operating condition; and

changing one or both of a number of parity bits stored in the memory array and an amount of duplicated data stored in the memory array according to a determined level of memory cell defectivity.

8. The method of claim 7 ,

wherein monitoring the operating conditions includes determining a level of memory cell defectivity; and

wherein changing the one or more operating conditions includes changing a number of memory cells subject to error detection according to a determined level of memory cell defectivity.

9. The method of claim 7 ,

wherein monitoring the operating conditions includes monitoring memory cell access rate; and

wherein changing the one or more operating conditions includes changing an access policy to memory cell cache by the memory access requests according to a determined memory cell access rate.

10. The method of claim 9 , changing the access policy to memory cell cache includes reallocating memory cells in a single level cell (SLC) cache to multiple level cell (MLC) storage.

11. The method of claim 7 ,

wherein monitoring the operating conditions includes monitoring the operating conditions for memory cell endurance; and

wherein changing the one or more operating conditions includes changing access to a number of single level cells (SLCs) and multiple level cell (MLCs) given to the memory access requests according to a determined operating condition of the memory array for memory cell endurance.

12. The method of claim 7 ,

wherein monitoring the operating conditions includes monitoring the operating conditions for memory cell endurance; and

wherein changing the one or more operating conditions includes changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for the memory access request, and an amount of duplicated data written as part of the memory access request according to a determined operating condition of the memory array for memory cell endurance.

13. The method of claim 7 ,

wherein determining the performance parameters includes determining power consumption by the memory array in responding to the memory access requests; and

wherein changing the one or more operating conditions includes changing one or more of a number of memory cells subject to error detection, an amount of duplicated data written to the memory array, a number of parity bits stored, and an access policy to memory cell cache granted to the memory access requests according to a determined power consumption.

14. A system comprising:

a host device; and

a memory device, the memory device including:

a memory array including memory cells;

an interface configured to receive memory access requests from the host device;

a memory control unit operatively coupled to the memory array and the interface, the memory control unit comprising a processor configured to execute instructions stored on the memory device that, when executed by the processor, cause the processor to:

control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including a memory cell defectivity protocol and boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption;

monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, power consumption, and memory cell endurance;

determine when a boundary condition for one of the multiple operating conditions is met;

in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a changed boundary condition of a second monitored operating condition;

and establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for the memory access request, and an amount of duplicated data written as part of the memory access request according to a determined operating condition of the memory array for memory cell endurance.

15. The system of claim 14 ,

wherein the processor is configured to execute instructions that cause the processor to:

monitor an activation rate at which the memory cell defectivity protocol is activated; and establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for a memory access request, and an amount of duplicated data written as part of the memory access request in response to a determined memory cell defectivity protocol activation rate.

16. The system of claim 14 , wherein the processor is configured to execute instructions that cause the processor to:

monitor a rate of P/E cycles requested by the host device; and

establish the second memory management protocol by changing an access policy to memory cell cache by the memory access requests according to a determined rate of P/E cycles.

17. The system of claim 14 , wherein the processor is configured to execute instructions that cause the processor to:

monitor operating conditions of the memory array for memory cell endurance; and

establish the second memory management protocol by changing access to a number of single level cells (SLCs) and multiple level cell (MLCs) given to the memory access requests according to a determined operating condition of the memory array for memory cell endurance.

18. The system of claim 14 , wherein the processor is configured to execute instructions that cause the processor to:

establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection, an amount of duplicated data written to the memory array, a number of parity bits stored, and an access policy to memory cell cache granted to the memory access requests according to a determined operating condition of the memory array for power consumption.